Lines Matching refs:phy_regmap
88 struct regmap *phy_regmap; member
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
113 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1, in ltq_vrx200_pcie_phy_common_setup()
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706); in ltq_vrx200_pcie_phy_common_setup()
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff); in ltq_vrx200_pcie_phy_common_setup()
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810); in ltq_vrx200_pcie_phy_common_setup()
127 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00, in ltq_vrx200_pcie_phy_common_setup()
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00); in ltq_vrx200_pcie_phy_common_setup()
134 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096); in ltq_vrx200_pcie_phy_common_setup()
135 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707); in ltq_vrx200_pcie_phy_common_setup()
138 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235); in ltq_vrx200_pcie_phy_common_setup()
145 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3, in pcie_phy_36mhz_mode_setup()
148 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3, in pcie_phy_36mhz_mode_setup()
151 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
155 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
159 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, in pcie_phy_36mhz_mode_setup()
163 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, in pcie_phy_36mhz_mode_setup()
167 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4); in pcie_phy_36mhz_mode_setup()
169 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2, in pcie_phy_36mhz_mode_setup()
175 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002); in pcie_phy_36mhz_mode_setup()
176 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04); in pcie_phy_36mhz_mode_setup()
177 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3); in pcie_phy_36mhz_mode_setup()
178 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72); in pcie_phy_36mhz_mode_setup()
187 ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS, in ltq_vrx200_pcie_phy_wait_for_pll()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
232 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe); in ltq_vrx200_pcie_phy_apply_workarounds()
233 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe); in ltq_vrx200_pcie_phy_apply_workarounds()
234 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601); in ltq_vrx200_pcie_phy_apply_workarounds()
236 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001); in ltq_vrx200_pcie_phy_apply_workarounds()
239 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe); in ltq_vrx200_pcie_phy_apply_workarounds()
240 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe); in ltq_vrx200_pcie_phy_apply_workarounds()
241 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601); in ltq_vrx200_pcie_phy_apply_workarounds()
243 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001); in ltq_vrx200_pcie_phy_apply_workarounds()
416 priv->phy_regmap = devm_regmap_init_mmio(dev, base, ®map_config); in ltq_vrx200_pcie_phy_probe()
417 if (IS_ERR(priv->phy_regmap)) in ltq_vrx200_pcie_phy_probe()
418 return PTR_ERR(priv->phy_regmap); in ltq_vrx200_pcie_phy_probe()