Lines Matching refs:PORT_REGS
79 #define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000) macro
121 reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
125 writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
128 reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
131 writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
134 reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG); in mvebu_cp110_utmi_port_setup()
137 writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG); in mvebu_cp110_utmi_port_setup()
140 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG); in mvebu_cp110_utmi_port_setup()
143 writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG); in mvebu_cp110_utmi_port_setup()
149 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG); in mvebu_cp110_utmi_port_setup()
152 writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG); in mvebu_cp110_utmi_port_setup()
158 reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG); in mvebu_cp110_utmi_port_setup()
161 writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG); in mvebu_cp110_utmi_port_setup()
218 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); in mvebu_cp110_utmi_phy_power_on()
220 writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); in mvebu_cp110_utmi_phy_power_on()
233 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); in mvebu_cp110_utmi_phy_power_on()
235 writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); in mvebu_cp110_utmi_phy_power_on()
238 ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg, in mvebu_cp110_utmi_phy_power_on()
247 ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg, in mvebu_cp110_utmi_phy_power_on()
256 ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg, in mvebu_cp110_utmi_phy_power_on()