Lines Matching refs:val
554 u32 val; in sds_wr() local
564 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
565 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
567 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
576 u32 val; in sds_rd() local
584 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
585 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
588 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
597 u32 val; in cmu_wr() local
606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
607 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
627 u32 val; in cmu_toggle1to0() local
629 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
630 val |= bits; in cmu_toggle1to0()
631 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
632 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
633 val &= ~bits; in cmu_toggle1to0()
634 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
640 u32 val; in cmu_clrbits() local
642 cmu_rd(ctx, cmu_type, reg, &val); in cmu_clrbits()
643 val &= ~bits; in cmu_clrbits()
644 cmu_wr(ctx, cmu_type, reg, val); in cmu_clrbits()
650 u32 val; in cmu_setbits() local
652 cmu_rd(ctx, cmu_type, reg, &val); in cmu_setbits()
653 val |= bits; in cmu_setbits()
654 cmu_wr(ctx, cmu_type, reg, val); in cmu_setbits()
660 u32 val; in serdes_wr() local
667 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in serdes_wr()
669 val); in serdes_wr()
686 u32 val; in serdes_clrbits() local
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
689 val &= ~bits; in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
696 u32 val; in serdes_setbits() local
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
699 val |= bits; in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
707 u32 val; in xgene_phy_cfg_cmu_clk_type() local
710 cmu_rd(ctx, cmu_type, CMU_REG12, &val); in xgene_phy_cfg_cmu_clk_type()
711 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
712 cmu_wr(ctx, cmu_type, CMU_REG12, val); in xgene_phy_cfg_cmu_clk_type()
720 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
721 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
722 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
724 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
725 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
726 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
730 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
731 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
732 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
734 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
735 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
736 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
745 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
746 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
747 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
749 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
750 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
751 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
761 u32 val; in xgene_phy_sata_cfg_cmu_core() local
766 cmu_rd(ctx, cmu_type, CMU_REG34, &val); in xgene_phy_sata_cfg_cmu_core()
767 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
768 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); in xgene_phy_sata_cfg_cmu_core()
769 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
770 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); in xgene_phy_sata_cfg_cmu_core()
771 cmu_wr(ctx, cmu_type, CMU_REG34, val); in xgene_phy_sata_cfg_cmu_core()
775 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_sata_cfg_cmu_core()
777 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
779 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
780 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_sata_cfg_cmu_core()
783 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_sata_cfg_cmu_core()
784 val = CMU_REG1_PLL_CP_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
786 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); in xgene_phy_sata_cfg_cmu_core()
788 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
790 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
792 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
793 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_sata_cfg_cmu_core()
799 cmu_rd(ctx, cmu_type, CMU_REG2, &val); in xgene_phy_sata_cfg_cmu_core()
801 val = CMU_REG2_PLL_LFRES_SET(val, 0xa); in xgene_phy_sata_cfg_cmu_core()
804 val = CMU_REG2_PLL_LFRES_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
811 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); in xgene_phy_sata_cfg_cmu_core()
812 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); in xgene_phy_sata_cfg_cmu_core()
814 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); in xgene_phy_sata_cfg_cmu_core()
815 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); in xgene_phy_sata_cfg_cmu_core()
817 cmu_wr(ctx, cmu_type, CMU_REG2, val); in xgene_phy_sata_cfg_cmu_core()
820 cmu_rd(ctx, cmu_type, CMU_REG3, &val); in xgene_phy_sata_cfg_cmu_core()
822 val = CMU_REG3_VCOVARSEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
823 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); in xgene_phy_sata_cfg_cmu_core()
825 val = CMU_REG3_VCOVARSEL_SET(val, 0xF); in xgene_phy_sata_cfg_cmu_core()
827 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
829 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); in xgene_phy_sata_cfg_cmu_core()
830 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
832 cmu_wr(ctx, cmu_type, CMU_REG3, val); in xgene_phy_sata_cfg_cmu_core()
835 cmu_rd(ctx, cmu_type, CMU_REG26, &val); in xgene_phy_sata_cfg_cmu_core()
836 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
837 cmu_wr(ctx, cmu_type, CMU_REG26, val); in xgene_phy_sata_cfg_cmu_core()
840 cmu_rd(ctx, cmu_type, CMU_REG5, &val); in xgene_phy_sata_cfg_cmu_core()
841 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
842 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
844 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
846 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
847 cmu_wr(ctx, cmu_type, CMU_REG5, val); in xgene_phy_sata_cfg_cmu_core()
850 cmu_rd(ctx, cmu_type, CMU_REG6, &val); in xgene_phy_sata_cfg_cmu_core()
851 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); in xgene_phy_sata_cfg_cmu_core()
852 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); in xgene_phy_sata_cfg_cmu_core()
853 cmu_wr(ctx, cmu_type, CMU_REG6, val); in xgene_phy_sata_cfg_cmu_core()
857 cmu_rd(ctx, cmu_type, CMU_REG9, &val); in xgene_phy_sata_cfg_cmu_core()
858 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, in xgene_phy_sata_cfg_cmu_core()
860 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, in xgene_phy_sata_cfg_cmu_core()
862 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
864 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
865 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); in xgene_phy_sata_cfg_cmu_core()
867 cmu_wr(ctx, cmu_type, CMU_REG9, val); in xgene_phy_sata_cfg_cmu_core()
870 cmu_rd(ctx, cmu_type, CMU_REG10, &val); in xgene_phy_sata_cfg_cmu_core()
871 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
872 cmu_wr(ctx, cmu_type, CMU_REG10, val); in xgene_phy_sata_cfg_cmu_core()
876 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_sata_cfg_cmu_core()
877 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
878 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
880 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
882 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
883 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_sata_cfg_cmu_core()
886 cmu_rd(ctx, cmu_type, CMU_REG30, &val); in xgene_phy_sata_cfg_cmu_core()
887 val = CMU_REG30_PCIE_MODE_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
888 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
889 cmu_wr(ctx, cmu_type, CMU_REG30, val); in xgene_phy_sata_cfg_cmu_core()
894 cmu_rd(ctx, cmu_type, CMU_REG32, &val); in xgene_phy_sata_cfg_cmu_core()
895 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
897 val = CMU_REG32_IREF_ADJ_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
899 val = CMU_REG32_IREF_ADJ_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
900 cmu_wr(ctx, cmu_type, CMU_REG32, val); in xgene_phy_sata_cfg_cmu_core()
915 u32 val; in xgene_phy_ssc_enable() local
918 cmu_rd(ctx, cmu_type, CMU_REG35, &val); in xgene_phy_ssc_enable()
919 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); in xgene_phy_ssc_enable()
920 cmu_wr(ctx, cmu_type, CMU_REG35, val); in xgene_phy_ssc_enable()
923 cmu_rd(ctx, cmu_type, CMU_REG36, &val); in xgene_phy_ssc_enable()
924 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); in xgene_phy_ssc_enable()
925 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); in xgene_phy_ssc_enable()
926 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); in xgene_phy_ssc_enable()
927 cmu_wr(ctx, cmu_type, CMU_REG36, val); in xgene_phy_ssc_enable()
940 u32 val; in xgene_phy_sata_cfg_lanes() local
949 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
950 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
951 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
952 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
953 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
956 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
957 val = RXTX_REG1_RXACVCM_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
958 val = RXTX_REG1_CTLE_EQ_SET(val, in xgene_phy_sata_cfg_lanes()
961 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
966 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
967 val = RXTX_REG2_VTT_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
968 val = RXTX_REG2_VTT_SEL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
969 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
970 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
973 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
974 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); in xgene_phy_sata_cfg_lanes()
975 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
978 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
979 val = RXTX_REG1_RXVREG1_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
980 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
985 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
986 val = RXTX_REG5_TX_CN1_SET(val, in xgene_phy_sata_cfg_lanes()
989 val = RXTX_REG5_TX_CP1_SET(val, in xgene_phy_sata_cfg_lanes()
992 val = RXTX_REG5_TX_CN2_SET(val, in xgene_phy_sata_cfg_lanes()
995 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
998 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
999 val = RXTX_REG6_TXAMP_CNTL_SET(val, in xgene_phy_sata_cfg_lanes()
1002 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1003 val = RXTX_REG6_TX_IDLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1004 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1005 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1010 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1011 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); in xgene_phy_sata_cfg_lanes()
1012 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1015 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1016 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1017 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1018 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1019 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1020 val = RXTX_REG8_SD_VREF_SET(val, 0x4); in xgene_phy_sata_cfg_lanes()
1021 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1024 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1025 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1026 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1029 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1030 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1031 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1032 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1033 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1036 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1037 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1038 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1039 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1048 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1049 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1050 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1051 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1053 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1054 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1060 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1061 val = RXTX_REG89_MU_TH7_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1062 val = RXTX_REG89_MU_TH8_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1063 val = RXTX_REG89_MU_TH9_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1064 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1070 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1071 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1072 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1073 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1074 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1080 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1081 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1082 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1083 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1084 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1087 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1088 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1089 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1093 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1094 val = RXTX_REG125_SIGN_PQ_SET(val, in xgene_phy_sata_cfg_lanes()
1097 val = RXTX_REG125_PQ_REG_SET(val, in xgene_phy_sata_cfg_lanes()
1100 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1101 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1103 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1104 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1105 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1107 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1108 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1109 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1111 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1112 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1113 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1115 val = RXTX_REG145_RXES_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1116 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1118 val = RXTX_REG145_RXES_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1119 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1121 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1140 u32 val; in xgene_phy_cal_rdy_chk() local
1154 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cal_rdy_chk()
1155 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1156 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cal_rdy_chk()
1180 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1181 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); in xgene_phy_cal_rdy_chk()
1182 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1183 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1191 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1192 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); in xgene_phy_cal_rdy_chk()
1193 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1194 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1198 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1199 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); in xgene_phy_cal_rdy_chk()
1200 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1201 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1209 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1210 if (CMU_REG7_PLL_CALIB_DONE_RD(val)) in xgene_phy_cal_rdy_chk()
1219 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1221 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); in xgene_phy_cal_rdy_chk()
1222 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { in xgene_phy_cal_rdy_chk()
1229 cmu_rd(ctx, cmu_type, CMU_REG15, &val); in xgene_phy_cal_rdy_chk()
1230 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1238 u32 val; in xgene_phy_pdwn_force_vco() local
1242 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_pdwn_force_vco()
1243 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_pdwn_force_vco()
1244 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_pdwn_force_vco()
1256 u32 val; in xgene_phy_hw_init_sata() local
1263 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ in xgene_phy_hw_init_sata()
1272 val = readl(sds_base + SATA_ENET_SDS_CTL1); in xgene_phy_hw_init_sata()
1273 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, in xgene_phy_hw_init_sata()
1275 writel(val, sds_base + SATA_ENET_SDS_CTL1); in xgene_phy_hw_init_sata()
1278 val = readl(sds_base + SATA_ENET_SDS_CTL0); in xgene_phy_hw_init_sata()
1279 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); in xgene_phy_hw_init_sata()
1280 writel(val, sds_base + SATA_ENET_SDS_CTL0); in xgene_phy_hw_init_sata()
1296 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); in xgene_phy_hw_init_sata()
1297 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1298 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1299 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); in xgene_phy_hw_init_sata()
1348 u32 val; in xgene_phy_force_lat_summer_cal() member
1406 serdes_reg[i].val); in xgene_phy_force_lat_summer_cal()
1435 u32 val; in xgene_phy_gen_avg_val() local
1459 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1460 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1461 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1462 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); in xgene_phy_gen_avg_val()
1464 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1465 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1466 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1467 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); in xgene_phy_gen_avg_val()
1469 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1470 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1471 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1473 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1474 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1475 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1477 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1478 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); in xgene_phy_gen_avg_val()
1511 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1512 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1514 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1516 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1518 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1519 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1521 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1523 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1525 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1526 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1528 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1530 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1532 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1533 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1535 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1537 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1540 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1541 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, in xgene_phy_gen_avg_val()
1543 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1559 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1560 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1561 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1564 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1565 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1567 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1571 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); in xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()