Lines Matching refs:writel
190 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | in qcom_edp_phy_init()
195 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_phy_init()
197 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
200 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | in qcom_edp_phy_init()
210 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
212 writel(0x00, edp->edp + DP_PHY_AUX_CFG0); in qcom_edp_phy_init()
213 writel(0x13, edp->edp + DP_PHY_AUX_CFG1); in qcom_edp_phy_init()
214 writel(0x24, edp->edp + DP_PHY_AUX_CFG2); in qcom_edp_phy_init()
215 writel(0x00, edp->edp + DP_PHY_AUX_CFG3); in qcom_edp_phy_init()
216 writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); in qcom_edp_phy_init()
217 writel(0x26, edp->edp + DP_PHY_AUX_CFG5); in qcom_edp_phy_init()
218 writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); in qcom_edp_phy_init()
219 writel(0x03, edp->edp + DP_PHY_AUX_CFG7); in qcom_edp_phy_init()
220 writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); in qcom_edp_phy_init()
221 writel(0x03, edp->edp + DP_PHY_AUX_CFG9); in qcom_edp_phy_init()
223 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | in qcom_edp_phy_init()
268 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
269 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
270 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
272 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
273 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
274 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
317 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); in qcom_edp_configure_ssc()
318 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); in qcom_edp_configure_ssc()
319 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); in qcom_edp_configure_ssc()
320 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); in qcom_edp_configure_ssc()
321 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_configure_ssc()
322 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_configure_ssc()
379 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); in qcom_edp_configure_pll()
380 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); in qcom_edp_configure_pll()
381 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); in qcom_edp_configure_pll()
382 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); in qcom_edp_configure_pll()
383 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); in qcom_edp_configure_pll()
384 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); in qcom_edp_configure_pll()
385 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); in qcom_edp_configure_pll()
386 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); in qcom_edp_configure_pll()
387 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); in qcom_edp_configure_pll()
388 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); in qcom_edp_configure_pll()
389 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); in qcom_edp_configure_pll()
390 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); in qcom_edp_configure_pll()
391 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); in qcom_edp_configure_pll()
392 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); in qcom_edp_configure_pll()
393 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); in qcom_edp_configure_pll()
394 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); in qcom_edp_configure_pll()
395 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); in qcom_edp_configure_pll()
396 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_configure_pll()
397 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_configure_pll()
398 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); in qcom_edp_configure_pll()
399 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); in qcom_edp_configure_pll()
400 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); in qcom_edp_configure_pll()
402 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); in qcom_edp_configure_pll()
403 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); in qcom_edp_configure_pll()
404 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); in qcom_edp_configure_pll()
405 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_configure_pll()
406 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); in qcom_edp_configure_pll()
407 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); in qcom_edp_configure_pll()
408 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); in qcom_edp_configure_pll()
444 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); in qcom_edp_set_vco_div()
461 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | in qcom_edp_phy_power_on()
465 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on()
475 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
476 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
477 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
478 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
491 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); in qcom_edp_phy_power_on()
492 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); in qcom_edp_phy_power_on()
495 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
496 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
497 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
498 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
499 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
502 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
503 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
504 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
505 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
506 writel(0x04, edp->tx1 + TXn_TX_BAND); in qcom_edp_phy_power_on()
512 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
513 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
514 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
515 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
517 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_edp_phy_power_on()
524 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
525 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
526 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
527 writel(0x00, edp->tx0 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
528 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
529 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
530 writel(0x00, edp->tx1 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
531 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
532 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
533 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
534 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
535 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
536 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
538 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
539 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
540 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
541 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
563 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
564 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
565 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
566 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
567 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
569 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
572 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
589 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_off()