Lines Matching refs:qphy
52 struct qcom_phy *qphy = phy_get_drvdata(phy); in qcom_pcie2_phy_init() local
55 ret = reset_control_deassert(qphy->phy_reset); in qcom_pcie2_phy_init()
57 dev_err(qphy->dev, "cannot deassert pipe reset\n"); in qcom_pcie2_phy_init()
61 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_init()
63 reset_control_assert(qphy->phy_reset); in qcom_pcie2_phy_init()
70 struct qcom_phy *qphy = phy_get_drvdata(phy); in qcom_pcie2_phy_power_on() local
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
82 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
84 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
87 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
89 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
94 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
96 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
99 val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); in qcom_pcie2_phy_power_on()
102 writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); in qcom_pcie2_phy_power_on()
104 val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); in qcom_pcie2_phy_power_on()
107 writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); in qcom_pcie2_phy_power_on()
110 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1); in qcom_pcie2_phy_power_on()
113 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1); in qcom_pcie2_phy_power_on()
115 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2); in qcom_pcie2_phy_power_on()
118 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2); in qcom_pcie2_phy_power_on()
120 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3); in qcom_pcie2_phy_power_on()
123 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3); in qcom_pcie2_phy_power_on()
126 val = readl(qphy->base + PCIE20_PARF_CONFIGBITS); in qcom_pcie2_phy_power_on()
129 writel(val, qphy->base + PCIE20_PARF_CONFIGBITS); in qcom_pcie2_phy_power_on()
132 val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3); in qcom_pcie2_phy_power_on()
135 writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3); in qcom_pcie2_phy_power_on()
138 val = readl(qphy->base + PCIE20_PARF_PCS_CTRL); in qcom_pcie2_phy_power_on()
140 writel(val, qphy->base + PCIE20_PARF_PCS_CTRL); in qcom_pcie2_phy_power_on()
143 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
145 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
149 ret = reset_control_deassert(qphy->pipe_reset); in qcom_pcie2_phy_power_on()
151 dev_err(qphy->dev, "cannot deassert pipe reset\n"); in qcom_pcie2_phy_power_on()
155 clk_set_rate(qphy->pipe_clk, 250000000); in qcom_pcie2_phy_power_on()
157 ret = clk_prepare_enable(qphy->pipe_clk); in qcom_pcie2_phy_power_on()
159 dev_err(qphy->dev, "failed to enable pipe clock\n"); in qcom_pcie2_phy_power_on()
163 ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val, in qcom_pcie2_phy_power_on()
166 dev_err(qphy->dev, "phy initialization failed\n"); in qcom_pcie2_phy_power_on()
174 struct qcom_phy *qphy = phy_get_drvdata(phy); in qcom_pcie2_phy_power_off() local
177 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_off()
179 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_off()
181 clk_disable_unprepare(qphy->pipe_clk); in qcom_pcie2_phy_power_off()
182 reset_control_assert(qphy->pipe_reset); in qcom_pcie2_phy_power_off()
189 struct qcom_phy *qphy = phy_get_drvdata(phy); in qcom_pcie2_phy_exit() local
191 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_exit()
192 reset_control_assert(qphy->phy_reset); in qcom_pcie2_phy_exit()
223 static int phy_pipe_clksrc_register(struct qcom_phy *qphy) in phy_pipe_clksrc_register() argument
225 struct device_node *np = qphy->dev->of_node; in phy_pipe_clksrc_register()
232 dev_err(qphy->dev, "%s: No clock-output-names\n", np->name); in phy_pipe_clksrc_register()
236 fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL); in phy_pipe_clksrc_register()
246 ret = devm_clk_hw_register(qphy->dev, &fixed->hw); in phy_pipe_clksrc_register()
250 return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw); in phy_pipe_clksrc_register()
256 struct qcom_phy *qphy; in qcom_pcie2_phy_probe() local
261 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); in qcom_pcie2_phy_probe()
262 if (!qphy) in qcom_pcie2_phy_probe()
265 qphy->dev = dev; in qcom_pcie2_phy_probe()
266 qphy->base = devm_platform_ioremap_resource(pdev, 0); in qcom_pcie2_phy_probe()
267 if (IS_ERR(qphy->base)) in qcom_pcie2_phy_probe()
268 return PTR_ERR(qphy->base); in qcom_pcie2_phy_probe()
270 ret = phy_pipe_clksrc_register(qphy); in qcom_pcie2_phy_probe()
276 qphy->vregs[0].supply = "vdda-vp"; in qcom_pcie2_phy_probe()
277 qphy->vregs[1].supply = "vdda-vph"; in qcom_pcie2_phy_probe()
278 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_probe()
282 qphy->pipe_clk = devm_clk_get(dev, NULL); in qcom_pcie2_phy_probe()
283 if (IS_ERR(qphy->pipe_clk)) { in qcom_pcie2_phy_probe()
285 return PTR_ERR(qphy->pipe_clk); in qcom_pcie2_phy_probe()
288 qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); in qcom_pcie2_phy_probe()
289 if (IS_ERR(qphy->phy_reset)) { in qcom_pcie2_phy_probe()
291 return PTR_ERR(qphy->phy_reset); in qcom_pcie2_phy_probe()
294 qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); in qcom_pcie2_phy_probe()
295 if (IS_ERR(qphy->pipe_reset)) { in qcom_pcie2_phy_probe()
297 return PTR_ERR(qphy->pipe_reset); in qcom_pcie2_phy_probe()
306 phy_set_drvdata(phy, qphy); in qcom_pcie2_phy_probe()