Lines Matching refs:UPDATE
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
37 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
39 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
54 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
56 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
58 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
60 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
64 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
66 #define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
69 #define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
71 #define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
74 #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
76 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
78 #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
82 #define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
84 #define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
86 #define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
89 #define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
91 #define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
96 #define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
97 #define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
98 #define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
99 #define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
102 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
104 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
106 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
108 #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
109 #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
111 #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
112 #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
123 #define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4)
124 #define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0)
126 #define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4)
127 #define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0)
135 #define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)
139 #define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
144 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)
146 #define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)
148 #define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
151 #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0)
153 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)
155 #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4)
159 #define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
161 #define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
165 #define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
167 #define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
175 #define RK3328_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
176 #define RK3328_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
178 #define RK3328_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
199 #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
201 #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
203 #define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
204 #define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)
205 #define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1)
206 #define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1)
222 #define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0)
224 #define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0)
226 #define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0)