Lines Matching refs:PIC32_SET
1819 writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); in pic32_gpio_direction_input()
1838 writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); in pic32_gpio_set()
1940 writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); in pic32_pinconf_set()
1944 writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); in pic32_pinconf_set()
1952 writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); in pic32_pinconf_set()
1956 writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); in pic32_pinconf_set()
2017 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_unmask()
2038 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2042 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2048 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2050 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2054 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2056 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2058 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()