Lines Matching refs:pctrl
64 struct pinctrl_dev *pctrl; member
87 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
90 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
95 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, in MSM_ACCESSOR()
109 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
114 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_groups_count() local
116 return pctrl->soc->ngroups; in msm_get_groups_count()
122 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
124 return pctrl->soc->groups[group].name; in msm_get_group_name()
132 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
134 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
135 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
149 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
150 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
157 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
159 return pctrl->soc->nfunctions; in msm_get_functions_count()
165 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
167 return pctrl->soc->functions[function].name; in msm_get_function_name()
175 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
177 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
178 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
186 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
187 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
190 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
191 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
197 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
219 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
222 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
224 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
233 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
234 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
238 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
241 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
256 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
258 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
261 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
266 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
269 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
281 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
282 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
288 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
300 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
353 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
361 g = &pctrl->soc->groups[group]; in msm_config_group_get()
363 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
367 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
383 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
391 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
414 val = msm_readl_io(pctrl, g); in msm_config_group_get()
438 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
448 g = &pctrl->soc->groups[group]; in msm_config_group_set()
454 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
467 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
473 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
492 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
493 val = msm_readl_io(pctrl, g); in msm_config_group_set()
498 msm_writel_io(val, pctrl, g); in msm_config_group_set()
499 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
509 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
516 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
520 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
521 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
524 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
525 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
540 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
544 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
546 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
548 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
550 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
552 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
560 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
564 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
566 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
568 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
573 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
575 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
577 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
579 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
586 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
590 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
592 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
601 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
604 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
606 val = msm_readl_io(pctrl, g); in msm_gpio_get()
613 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
617 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
619 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
621 val = msm_readl_io(pctrl, g); in msm_gpio_set()
626 msm_writel_io(val, pctrl, g); in msm_gpio_set()
628 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
640 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
665 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
666 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
667 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
674 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
690 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
714 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
717 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
724 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
734 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
745 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
747 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
791 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
800 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
802 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
804 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
806 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
807 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
811 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
818 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
826 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
829 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
831 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
833 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
858 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
860 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
862 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
868 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_unmask() local
876 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
879 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
881 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
883 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
886 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
888 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
890 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
896 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
903 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
910 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
915 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
933 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
934 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
940 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
953 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
964 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
970 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
974 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
975 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
980 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
982 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
984 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
986 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
987 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
989 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1004 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
1007 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1008 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1014 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
1021 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1030 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1031 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1036 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1038 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1044 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1046 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1052 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1053 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1063 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1067 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1070 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1078 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1127 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1135 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1137 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1138 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1140 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1153 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1161 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1164 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1170 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1176 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1214 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1216 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1225 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1227 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1237 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1249 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1250 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1251 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1271 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1278 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1279 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1289 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1291 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1294 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1317 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1322 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1329 chip = &pctrl->chip; in msm_gpio_init()
1332 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1333 chip->parent = pctrl->dev; in msm_gpio_init()
1335 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1338 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1351 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1352 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1353 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1360 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1362 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1368 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1370 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1372 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1386 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1387 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1388 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1390 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1391 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1402 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1404 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1416 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1419 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1421 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1423 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1424 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1425 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1426 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1428 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1436 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1438 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1443 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1445 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1456 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1461 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1462 if (!pctrl) in msm_pinctrl_probe()
1465 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1466 pctrl->soc = soc_data; in msm_pinctrl_probe()
1467 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1468 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1469 pctrl->dev->of_node, in msm_pinctrl_probe()
1472 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1478 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1479 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1480 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1484 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1485 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1486 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1488 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1491 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1493 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1494 if (pctrl->irq < 0) in msm_pinctrl_probe()
1495 return pctrl->irq; in msm_pinctrl_probe()
1497 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1498 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1499 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1500 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1501 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1502 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1503 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1505 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1506 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1508 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1511 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1515 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1525 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1527 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1529 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()