Lines Matching refs:pctrl
127 struct pinctrl_dev *pctrl; member
167 static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl, in pm8xxx_mpp_update() argument
236 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_mpp_update()
238 dev_err(pctrl->dev, "failed to write register\n"); in pm8xxx_mpp_update()
245 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_groups_count() local
247 return pctrl->npins; in pm8xxx_get_groups_count()
262 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_group_pins() local
264 *pins = &pctrl->desc.pins[group].number; in pm8xxx_get_group_pins()
294 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_function_groups() local
297 *num_groups = pctrl->npins; in pm8xxx_get_function_groups()
305 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pinmux_set_mux() local
306 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux()
309 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_pinmux_set_mux()
325 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pin_config_get() local
326 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get()
375 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pin_config_set() local
376 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_set()
418 dev_err(pctrl->dev, in pm8xxx_pin_config_set()
425 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_pin_config_set()
447 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_direction_input() local
448 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_direction_input()
462 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_direction_input()
471 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_direction_output() local
472 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_direction_output()
488 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_direction_output()
495 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_get() local
496 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_get()
516 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_set() local
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_set()
521 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_set()
546 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_dbg_show_one() local
547 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_dbg_show_one()
645 static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, in pm8xxx_pin_populate() argument
654 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_pin_populate()
656 dev_err(pctrl->dev, "failed to read register\n"); in pm8xxx_pin_populate()
737 struct pm8xxx_mpp *pctrl = container_of(domain->host_data, in pm8xxx_mpp_domain_translate() local
742 fwspec->param[0] > pctrl->chip.ngpio) in pm8xxx_mpp_domain_translate()
799 struct pm8xxx_mpp *pctrl; in pm8xxx_mpp_probe() local
803 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in pm8xxx_mpp_probe()
804 if (!pctrl) in pm8xxx_mpp_probe()
807 pctrl->dev = &pdev->dev; in pm8xxx_mpp_probe()
808 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); in pm8xxx_mpp_probe()
810 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); in pm8xxx_mpp_probe()
811 if (!pctrl->regmap) { in pm8xxx_mpp_probe()
816 pctrl->desc = pm8xxx_pinctrl_desc; in pm8xxx_mpp_probe()
817 pctrl->desc.npins = pctrl->npins; in pm8xxx_mpp_probe()
820 pctrl->desc.npins, in pm8xxx_mpp_probe()
827 pctrl->desc.npins, in pm8xxx_mpp_probe()
833 for (i = 0; i < pctrl->desc.npins; i++) { in pm8xxx_mpp_probe()
836 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); in pm8xxx_mpp_probe()
844 pctrl->desc.pins = pins; in pm8xxx_mpp_probe()
846 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings); in pm8xxx_mpp_probe()
847 pctrl->desc.custom_params = pm8xxx_mpp_bindings; in pm8xxx_mpp_probe()
849 pctrl->desc.custom_conf_items = pm8xxx_conf_items; in pm8xxx_mpp_probe()
852 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in pm8xxx_mpp_probe()
853 if (IS_ERR(pctrl->pctrl)) { in pm8xxx_mpp_probe()
855 return PTR_ERR(pctrl->pctrl); in pm8xxx_mpp_probe()
858 pctrl->chip = pm8xxx_mpp_template; in pm8xxx_mpp_probe()
859 pctrl->chip.base = -1; in pm8xxx_mpp_probe()
860 pctrl->chip.parent = &pdev->dev; in pm8xxx_mpp_probe()
861 pctrl->chip.of_gpio_n_cells = 2; in pm8xxx_mpp_probe()
862 pctrl->chip.label = dev_name(pctrl->dev); in pm8xxx_mpp_probe()
863 pctrl->chip.ngpio = pctrl->npins; in pm8xxx_mpp_probe()
865 parent_node = of_irq_find_parent(pctrl->dev->of_node); in pm8xxx_mpp_probe()
874 pctrl->irq.name = "ssbi-mpp"; in pm8xxx_mpp_probe()
875 pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; in pm8xxx_mpp_probe()
876 pctrl->irq.irq_unmask = irq_chip_unmask_parent; in pm8xxx_mpp_probe()
877 pctrl->irq.irq_set_type = irq_chip_set_type_parent; in pm8xxx_mpp_probe()
878 pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; in pm8xxx_mpp_probe()
880 girq = &pctrl->chip.irq; in pm8xxx_mpp_probe()
881 girq->chip = &pctrl->irq; in pm8xxx_mpp_probe()
884 girq->fwnode = dev_fwnode(pctrl->dev); in pm8xxx_mpp_probe()
894 ret = gpiochip_add_data(&pctrl->chip, pctrl); in pm8xxx_mpp_probe()
900 ret = gpiochip_add_pin_range(&pctrl->chip, in pm8xxx_mpp_probe()
901 dev_name(pctrl->dev), in pm8xxx_mpp_probe()
902 0, 0, pctrl->chip.ngpio); in pm8xxx_mpp_probe()
904 dev_err(pctrl->dev, "failed to add pin range\n"); in pm8xxx_mpp_probe()
908 platform_set_drvdata(pdev, pctrl); in pm8xxx_mpp_probe()
915 gpiochip_remove(&pctrl->chip); in pm8xxx_mpp_probe()
922 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev); in pm8xxx_mpp_remove() local
924 gpiochip_remove(&pctrl->chip); in pm8xxx_mpp_remove()