Lines Matching refs:RCAR_GP_PIN
512 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
519 RCAR_GP_PIN(0, 1),
526 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
535 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
542 RCAR_GP_PIN(0, 8),
549 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
558 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
565 RCAR_GP_PIN(1, 0),
572 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
581 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
588 RCAR_GP_PIN(0, 14),
595 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
604 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
613 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
622 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
631 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
640 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
649 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
659 RCAR_GP_PIN(0, 17),
666 RCAR_GP_PIN(0, 18),
673 RCAR_GP_PIN(0, 19),
680 RCAR_GP_PIN(0, 20),
687 RCAR_GP_PIN(0, 11),
694 RCAR_GP_PIN(0, 15),
703 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
704 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
705 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
706 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
716 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
723 RCAR_GP_PIN(1, 23),
730 RCAR_GP_PIN(1, 24),
737 RCAR_GP_PIN(1, 20),
746 RCAR_GP_PIN(0, 14),
753 RCAR_GP_PIN(0, 11),
760 RCAR_GP_PIN(0, 15),
767 RCAR_GP_PIN(0, 16),
774 RCAR_GP_PIN(0, 13),
781 RCAR_GP_PIN(0, 12),
790 RCAR_GP_PIN(0, 8),
797 RCAR_GP_PIN(0, 10),
804 RCAR_GP_PIN(0, 17),
811 RCAR_GP_PIN(0, 18),
818 RCAR_GP_PIN(0, 7),
825 RCAR_GP_PIN(0, 6),
834 RCAR_GP_PIN(1, 5),
841 RCAR_GP_PIN(1, 4),
848 RCAR_GP_PIN(1, 2),
855 RCAR_GP_PIN(1, 3),
862 RCAR_GP_PIN(1, 7),
869 RCAR_GP_PIN(1, 6),
878 RCAR_GP_PIN(0, 1),
885 RCAR_GP_PIN(0, 9),
892 RCAR_GP_PIN(0, 4),
899 RCAR_GP_PIN(0, 5),
906 RCAR_GP_PIN(0, 3),
913 RCAR_GP_PIN(0, 2),
922 RCAR_GP_PIN(2, 15),
931 RCAR_GP_PIN(2, 16),
941 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
948 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
949 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
959 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
966 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
967 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
977 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
984 RCAR_GP_PIN(0, 8),
991 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1000 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1007 RCAR_GP_PIN(0, 14),
1014 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1030 RCAR_GP_PIN(0, 1),
1037 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
1046 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1053 RCAR_GP_PIN(1, 5),
1060 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
1069 RCAR_GP_PIN(0, 0),
1078 RCAR_GP_PIN(0, 11),
1085 RCAR_GP_PIN(0, 17),
1092 RCAR_GP_PIN(0, 18),
1099 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1106 RCAR_GP_PIN(3, 8),
1113 RCAR_GP_PIN(3, 12),
1120 RCAR_GP_PIN(3, 10),
1127 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
1134 RCAR_GP_PIN(3, 16),
1141 RCAR_GP_PIN(0, 1),
1148 RCAR_GP_PIN(0, 2),
1155 RCAR_GP_PIN(3, 18),
1162 RCAR_GP_PIN(3, 17),
1171 RCAR_GP_PIN(0, 15),
1178 RCAR_GP_PIN(0, 19),
1185 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1192 RCAR_GP_PIN(3, 6),
1199 RCAR_GP_PIN(3, 11),
1206 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1213 RCAR_GP_PIN(3, 13),
1220 RCAR_GP_PIN(0, 7),
1227 RCAR_GP_PIN(0, 6),
1234 RCAR_GP_PIN(3, 15),
1241 RCAR_GP_PIN(3, 14),
1250 RCAR_GP_PIN(0, 16),
1257 RCAR_GP_PIN(0, 20),
1264 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1271 RCAR_GP_PIN(3, 7),
1278 RCAR_GP_PIN(3, 9),
1285 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
1792 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
1793 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
1794 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
1795 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
1796 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
1797 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
1798 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
1799 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
1802 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
1803 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
1804 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
1805 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
1806 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
1807 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
1808 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
1809 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
1812 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
1813 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
1814 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
1815 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
1816 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
1819 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
1820 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
1821 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
1822 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
1823 { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
1824 { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
1825 { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
1826 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
1829 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
1830 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
1831 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
1832 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
1833 { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
1834 { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
1835 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
1836 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
1839 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
1840 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
1841 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
1842 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
1843 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
1844 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
1845 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
1846 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
1849 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
1852 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
1853 { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
1854 { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
1855 { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
1856 { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
1857 { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
1858 { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
1859 { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
1862 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
1863 { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
1864 { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
1865 { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
1866 { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
1867 { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
1868 { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
1869 { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
1872 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
1875 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
1876 { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
1877 { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
1878 { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
1879 { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
1880 { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
1881 { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
1882 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
1885 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
1886 { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
1887 { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
1888 { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
1889 { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
1890 { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
1891 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
1892 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
1895 { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
1896 { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
1897 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
1922 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20)) in r8a779f0_pin_to_pocctrl()
1926 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24)) in r8a779f0_pin_to_pocctrl()
1930 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18)) in r8a779f0_pin_to_pocctrl()
1938 [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
1939 [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
1940 [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */
1941 [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */
1942 [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
1943 [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
1944 [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */
1945 [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */
1946 [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */
1947 [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
1948 [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
1949 [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
1950 [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
1951 [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
1952 [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
1953 [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
1954 [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
1955 [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
1956 [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
1957 [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
1958 [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
1972 [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
1973 [ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
1974 [ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
1975 [ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
1976 [ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
1977 [ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
1978 [ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
1979 [ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
1980 [ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
1981 [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
1982 [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
1983 [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
1984 [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
1985 [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
1986 [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
1987 [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
1988 [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
1989 [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
1990 [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
1991 [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
1992 [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
1993 [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
1994 [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
1995 [23] = RCAR_GP_PIN(1, 23), /* SD_CD */
1996 [24] = RCAR_GP_PIN(1, 24), /* SD_WP */
2006 [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
2007 [ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
2008 [ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
2009 [ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
2010 [ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
2011 [ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
2012 [ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
2013 [ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
2014 [ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
2015 [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
2016 [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
2017 [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
2018 [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
2019 [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
2020 [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
2021 [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
2022 [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
2040 [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
2041 [ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
2042 [ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
2043 [ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
2044 [ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
2045 [ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
2046 [ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
2047 [ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
2048 [ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
2049 [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
2050 [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
2051 [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
2052 [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
2053 [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
2054 [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
2055 [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
2056 [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
2057 [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
2058 [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */