Lines Matching refs:RCAR_GP_PIN
1202 RCAR_GP_PIN(7, 4),
1209 RCAR_GP_PIN(7, 10),
1216 RCAR_GP_PIN(7, 5),
1223 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1233 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1234 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1235 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1236 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1237 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1238 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1250 RCAR_GP_PIN(7, 9),
1257 RCAR_GP_PIN(7, 0),
1264 RCAR_GP_PIN(7, 1),
1271 RCAR_GP_PIN(7, 2),
1280 RCAR_GP_PIN(6, 4),
1287 RCAR_GP_PIN(6, 1),
1294 RCAR_GP_PIN(6, 3),
1301 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1311 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1312 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1313 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1314 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1315 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1316 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1328 RCAR_GP_PIN(6, 20),
1335 RCAR_GP_PIN(6, 10),
1342 RCAR_GP_PIN(6, 11),
1349 RCAR_GP_PIN(6, 5),
1358 RCAR_GP_PIN(5, 3),
1365 RCAR_GP_PIN(5, 5),
1372 RCAR_GP_PIN(5, 4),
1379 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1389 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1390 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1391 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1392 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1393 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1394 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1406 RCAR_GP_PIN(5, 7),
1413 RCAR_GP_PIN(5, 0),
1420 RCAR_GP_PIN(5, 1),
1427 RCAR_GP_PIN(5, 2),
1436 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1445 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1454 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1463 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1472 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1481 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1490 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1499 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1508 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1517 RCAR_GP_PIN(2, 9),
1526 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1533 RCAR_GP_PIN(1, 15),
1540 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1549 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1556 RCAR_GP_PIN(0, 18),
1563 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1572 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1579 RCAR_GP_PIN(1, 10),
1586 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1595 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1602 RCAR_GP_PIN(8, 13),
1609 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1618 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1625 RCAR_GP_PIN(1, 25),
1632 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1641 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1648 RCAR_GP_PIN(1, 3),
1655 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1664 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1673 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1682 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1691 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1700 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1709 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1718 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1719 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1720 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1721 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1731 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1738 RCAR_GP_PIN(3, 11),
1745 RCAR_GP_PIN(3, 12),
1752 RCAR_GP_PIN(3, 4),
1761 RCAR_GP_PIN(1, 10),
1768 RCAR_GP_PIN(1, 8),
1775 RCAR_GP_PIN(1, 7),
1782 RCAR_GP_PIN(1, 6),
1789 RCAR_GP_PIN(1, 9),
1796 RCAR_GP_PIN(1, 11),
1805 RCAR_GP_PIN(1, 3),
1812 RCAR_GP_PIN(1, 2),
1819 RCAR_GP_PIN(1, 1),
1826 RCAR_GP_PIN(1, 0),
1833 RCAR_GP_PIN(1, 4),
1840 RCAR_GP_PIN(1, 5),
1849 RCAR_GP_PIN(0, 17),
1856 RCAR_GP_PIN(0, 15),
1863 RCAR_GP_PIN(0, 14),
1870 RCAR_GP_PIN(0, 13),
1877 RCAR_GP_PIN(0, 16),
1884 RCAR_GP_PIN(0, 18),
1893 RCAR_GP_PIN(0, 3),
1900 RCAR_GP_PIN(0, 6),
1907 RCAR_GP_PIN(0, 1),
1914 RCAR_GP_PIN(0, 2),
1921 RCAR_GP_PIN(0, 4),
1928 RCAR_GP_PIN(0, 5),
1937 RCAR_GP_PIN(1, 25),
1944 RCAR_GP_PIN(1, 28),
1951 RCAR_GP_PIN(1, 23),
1958 RCAR_GP_PIN(1, 24),
1965 RCAR_GP_PIN(1, 26),
1972 RCAR_GP_PIN(1, 27),
1981 RCAR_GP_PIN(0, 11),
1988 RCAR_GP_PIN(0, 9),
1995 RCAR_GP_PIN(0, 8),
2002 RCAR_GP_PIN(0, 7),
2009 RCAR_GP_PIN(0, 10),
2016 RCAR_GP_PIN(0, 12),
2025 RCAR_GP_PIN(4, 21),
2034 RCAR_GP_PIN(4, 22),
2044 RCAR_GP_PIN(1, 15),
2053 RCAR_GP_PIN(3, 13),
2062 RCAR_GP_PIN(2, 13),
2071 RCAR_GP_PIN(2, 14),
2080 RCAR_GP_PIN(1, 22),
2089 RCAR_GP_PIN(2, 15),
2098 RCAR_GP_PIN(2, 16),
2107 RCAR_GP_PIN(2, 17),
2116 RCAR_GP_PIN(2, 18),
2125 RCAR_GP_PIN(2, 19),
2134 RCAR_GP_PIN(1, 13),
2143 RCAR_GP_PIN(1, 14),
2152 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2159 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2160 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2170 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2177 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2178 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2188 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2195 RCAR_GP_PIN(1, 15),
2202 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2211 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2218 RCAR_GP_PIN(0, 18),
2225 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2234 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2241 RCAR_GP_PIN(1, 10),
2248 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2257 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2264 RCAR_GP_PIN(1, 4),
2271 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2280 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2287 RCAR_GP_PIN(1, 24),
2294 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2303 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2310 RCAR_GP_PIN(8, 8),
2317 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2326 RCAR_GP_PIN(1, 17),
2335 RCAR_GP_PIN(2, 8),
2342 RCAR_GP_PIN(2, 7),
2349 RCAR_GP_PIN(2, 12),
2356 RCAR_GP_PIN(2, 13),
2365 RCAR_GP_PIN(1, 25),
2372 RCAR_GP_PIN(1, 26),
2379 RCAR_GP_PIN(2, 0),
2386 RCAR_GP_PIN(2, 1),
2395 RCAR_GP_PIN(4, 4),
2402 RCAR_GP_PIN(4, 3),
2409 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2419 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2420 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2421 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2422 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2423 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2424 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2436 RCAR_GP_PIN(4, 20),
2443 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2450 RCAR_GP_PIN(4, 6),
2457 RCAR_GP_PIN(4, 5),
3619 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3620 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3621 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3622 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3623 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3624 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3625 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3626 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3629 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3630 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3631 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3632 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3633 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3634 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3635 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3636 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3639 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3640 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3641 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3644 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3645 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3646 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3647 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3648 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3649 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3650 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3651 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3654 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3655 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3656 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3657 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3658 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3659 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3660 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3661 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3664 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3665 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3666 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3667 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3668 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3669 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3670 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3671 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3674 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3675 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3676 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3677 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3678 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3681 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3682 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3683 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3684 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3685 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3686 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3687 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3688 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3691 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3692 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3693 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3694 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3695 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3696 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3697 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3698 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3701 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3702 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3703 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3704 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3707 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3708 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3709 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3710 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3711 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3712 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3713 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3714 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3717 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3718 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3719 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3720 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3721 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3722 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3723 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3724 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3727 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3728 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3729 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3730 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3731 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3732 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3733 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3734 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3737 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3738 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3739 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3740 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3741 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3742 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3745 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3746 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3747 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3748 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3749 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3750 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3751 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3752 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3755 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3756 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3757 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3758 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3759 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3760 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3761 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3762 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3765 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3766 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3767 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3768 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3769 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3770 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3771 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3772 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3775 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3778 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3779 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3780 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3781 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3782 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3783 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3784 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3785 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3788 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3789 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3790 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3791 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3792 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3793 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3794 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3795 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3798 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3799 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3800 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3801 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3802 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3805 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3806 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3807 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3808 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3809 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3810 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3811 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3812 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3815 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3816 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3817 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3818 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3819 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3820 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3821 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3822 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3825 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3826 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3827 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3828 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3829 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3832 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3833 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3834 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3835 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3836 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3837 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3838 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3839 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3842 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3843 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3844 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3845 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3846 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3847 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3848 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3849 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3852 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3853 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3854 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3855 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3856 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3859 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3860 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3861 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3862 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3863 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3864 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3865 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3866 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3869 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3870 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3871 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3872 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3873 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3874 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3907 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18)) in r8a779g0_pin_to_pocctrl()
3911 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) in r8a779g0_pin_to_pocctrl()
3915 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12)) in r8a779g0_pin_to_pocctrl()
3919 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13)) in r8a779g0_pin_to_pocctrl()
3927 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3928 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3929 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3930 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3931 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3932 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3933 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3934 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3935 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3936 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3937 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3938 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3939 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3940 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3941 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3942 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3943 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3944 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3945 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3961 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3962 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3963 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3964 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3965 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3966 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3967 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3968 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3969 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3970 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3971 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3972 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3973 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3974 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3975 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3976 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3977 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3978 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3979 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3980 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3981 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
3982 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
3983 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
3984 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
3985 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
3986 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
3987 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
3988 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
3989 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
3995 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
3996 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
3997 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
3998 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
3999 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4000 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4001 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4002 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4003 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4004 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4005 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4006 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4007 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4008 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4009 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4010 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4011 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4012 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4013 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4014 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4029 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4030 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4031 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4032 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4033 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4034 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4035 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4036 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4037 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4038 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4039 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4040 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4041 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4042 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4043 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4044 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4045 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4046 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4047 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4048 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4049 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4050 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4051 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4052 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4053 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4054 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4055 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4056 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4057 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4058 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4063 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4064 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4065 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4066 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4067 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4068 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4069 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4070 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4071 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4072 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4073 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4074 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4075 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4076 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4077 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4078 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4079 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4080 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4081 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4082 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4083 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4084 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4085 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4086 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4087 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4097 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4098 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4099 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4100 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4101 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4102 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4103 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4104 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4105 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4106 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4107 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4108 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4109 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4110 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4111 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4112 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4113 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4114 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4115 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4116 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4117 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4131 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4132 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4133 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4134 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4135 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4136 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4137 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4138 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4139 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4140 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4141 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4142 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4143 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4144 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4145 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4146 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4147 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4148 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4149 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4150 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4151 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4165 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4166 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4167 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4168 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4169 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4170 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4171 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4172 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4173 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4174 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4175 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4176 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4177 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4178 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4179 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4180 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4181 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4182 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4183 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4184 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4185 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4199 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4200 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4201 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4202 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4203 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4204 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4205 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4206 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4207 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4208 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4209 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4210 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4211 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4212 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */