Lines Matching refs:BIT
17 {"PSF9", BIT(0)},
18 {"RES_66", BIT(1)},
19 {"RES_67", BIT(2)},
20 {"RES_68", BIT(3)},
21 {"RES_69", BIT(4)},
22 {"RES_70", BIT(5)},
23 {"TBTLSX", BIT(6)},
38 {"USB2PLL_OFF_STS", BIT(18)},
39 {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
40 {"PCIe_Gen3PLL_OFF_STS", BIT(20)},
41 {"OPIOPLL_OFF_STS", BIT(21)},
42 {"OCPLL_OFF_STS", BIT(22)},
43 {"MainPLL_OFF_STS", BIT(23)},
44 {"MIPIPLL_OFF_STS", BIT(24)},
45 {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
46 {"AC_Ring_Osc_OFF_STS", BIT(26)},
47 {"MC_Ring_Osc_OFF_STS", BIT(27)},
48 {"SATAPLL_OFF_STS", BIT(29)},
49 {"XTAL_USB2PLL_OFF_STS", BIT(31)},
54 {"CSME_PG_STS", BIT(0)},
55 {"SATA_PG_STS", BIT(1)},
56 {"xHCI_PG_STS", BIT(2)},
57 {"UFSX2_PG_STS", BIT(3)},
58 {"OTG_PG_STS", BIT(5)},
59 {"SPA_PG_STS", BIT(6)},
60 {"SPB_PG_STS", BIT(7)},
61 {"SPC_PG_STS", BIT(8)},
62 {"SPD_PG_STS", BIT(9)},
63 {"SPE_PG_STS", BIT(10)},
64 {"SPF_PG_STS", BIT(11)},
65 {"LSX_PG_STS", BIT(13)},
66 {"P2SB_PG_STS", BIT(14)},
67 {"PSF_PG_STS", BIT(15)},
68 {"SBR_PG_STS", BIT(16)},
69 {"OPIDMI_PG_STS", BIT(17)},
70 {"THC0_PG_STS", BIT(18)},
71 {"THC1_PG_STS", BIT(19)},
72 {"GBETSN_PG_STS", BIT(20)},
73 {"GBE_PG_STS", BIT(21)},
74 {"LPSS_PG_STS", BIT(22)},
75 {"MMP_UFSX2_PG_STS", BIT(23)},
76 {"MMP_UFSX2B_PG_STS", BIT(24)},
77 {"FIA_PG_STS", BIT(25)},
82 {"ADSP_D3_STS", BIT(0)},
83 {"SATA_D3_STS", BIT(1)},
84 {"xHCI0_D3_STS", BIT(2)},
85 {"xDCI1_D3_STS", BIT(5)},
86 {"SDX_D3_STS", BIT(6)},
87 {"EMMC_D3_STS", BIT(7)},
88 {"IS_D3_STS", BIT(8)},
89 {"THC0_D3_STS", BIT(9)},
90 {"THC1_D3_STS", BIT(10)},
91 {"GBE_D3_STS", BIT(11)},
92 {"GBE_TSN_D3_STS", BIT(12)},
97 {"GPIO_COM0_VNN_REQ_STS", BIT(1)},
98 {"GPIO_COM1_VNN_REQ_STS", BIT(2)},
99 {"GPIO_COM2_VNN_REQ_STS", BIT(3)},
100 {"GPIO_COM3_VNN_REQ_STS", BIT(4)},
101 {"GPIO_COM4_VNN_REQ_STS", BIT(5)},
102 {"GPIO_COM5_VNN_REQ_STS", BIT(6)},
103 {"Audio_VNN_REQ_STS", BIT(7)},
104 {"ISH_VNN_REQ_STS", BIT(8)},
105 {"CNVI_VNN_REQ_STS", BIT(9)},
106 {"eSPI_VNN_REQ_STS", BIT(10)},
107 {"Display_VNN_REQ_STS", BIT(11)},
108 {"DTS_VNN_REQ_STS", BIT(12)},
109 {"SMBUS_VNN_REQ_STS", BIT(14)},
110 {"CSME_VNN_REQ_STS", BIT(15)},
111 {"SMLINK0_VNN_REQ_STS", BIT(16)},
112 {"SMLINK1_VNN_REQ_STS", BIT(17)},
113 {"CLINK_VNN_REQ_STS", BIT(20)},
114 {"DCI_VNN_REQ_STS", BIT(21)},
115 {"ITH_VNN_REQ_STS", BIT(22)},
116 {"CSME_VNN_REQ_STS", BIT(24)},
117 {"GBE_VNN_REQ_STS", BIT(25)},
122 {"CPU_C10_REQ_STS_0", BIT(0)},
123 {"PCIe_LPM_En_REQ_STS_3", BIT(3)},
124 {"ITH_REQ_STS_5", BIT(5)},
125 {"CNVI_REQ_STS_6", BIT(6)},
126 {"ISH_REQ_STS_7", BIT(7)},
127 {"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
128 {"PCIe_Clk_REQ_STS_12", BIT(12)},
129 {"MPHY_Core_DL_REQ_STS_16", BIT(16)},
130 {"Break-even_En_REQ_STS_17", BIT(17)},
131 {"Auto-demo_En_REQ_STS_18", BIT(18)},
132 {"MPHY_SUS_REQ_STS_22", BIT(22)},
133 {"xDCI_attached_REQ_STS_24", BIT(24)},
138 {"LSX_Wake0_En_STS", BIT(0)},
139 {"LSX_Wake0_Pol_STS", BIT(1)},
140 {"LSX_Wake1_En_STS", BIT(2)},
141 {"LSX_Wake1_Pol_STS", BIT(3)},
142 {"LSX_Wake2_En_STS", BIT(4)},
143 {"LSX_Wake2_Pol_STS", BIT(5)},
144 {"LSX_Wake3_En_STS", BIT(6)},
145 {"LSX_Wake3_Pol_STS", BIT(7)},
146 {"LSX_Wake4_En_STS", BIT(8)},
147 {"LSX_Wake4_Pol_STS", BIT(9)},
148 {"LSX_Wake5_En_STS", BIT(10)},
149 {"LSX_Wake5_Pol_STS", BIT(11)},
150 {"LSX_Wake6_En_STS", BIT(12)},
151 {"LSX_Wake6_Pol_STS", BIT(13)},
152 {"LSX_Wake7_En_STS", BIT(14)},
153 {"LSX_Wake7_Pol_STS", BIT(15)},
154 {"Intel_Se_IO_Wake0_En_STS", BIT(16)},
155 {"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
156 {"Intel_Se_IO_Wake1_En_STS", BIT(18)},
157 {"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
158 {"Int_Timer_SS_Wake0_En_STS", BIT(20)},
159 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
160 {"Int_Timer_SS_Wake1_En_STS", BIT(22)},
161 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
162 {"Int_Timer_SS_Wake2_En_STS", BIT(24)},
163 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
164 {"Int_Timer_SS_Wake3_En_STS", BIT(26)},
165 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
166 {"Int_Timer_SS_Wake4_En_STS", BIT(28)},
167 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
168 {"Int_Timer_SS_Wake5_En_STS", BIT(30)},
169 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},