Lines Matching refs:fpc
62 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc) in ftm_clear_write_protection() argument
66 regmap_read(fpc->regmap, FTM_FMS, &val); in ftm_clear_write_protection()
68 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); in ftm_clear_write_protection()
71 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc) in ftm_set_write_protection() argument
73 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); in ftm_set_write_protection()
91 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_request() local
93 ret = clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_request()
94 if (!ret && fpc->soc->has_enable_bits) { in fsl_pwm_request()
95 mutex_lock(&fpc->lock); in fsl_pwm_request()
96 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); in fsl_pwm_request()
97 mutex_unlock(&fpc->lock); in fsl_pwm_request()
105 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_free() local
107 if (fpc->soc->has_enable_bits) { in fsl_pwm_free()
108 mutex_lock(&fpc->lock); in fsl_pwm_free()
109 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); in fsl_pwm_free()
110 mutex_unlock(&fpc->lock); in fsl_pwm_free()
113 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_free()
116 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc, in fsl_pwm_ticks_to_ns() argument
122 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()
125 do_div(exval, rate >> fpc->period.clk_ps); in fsl_pwm_ticks_to_ns()
129 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_period_clk() argument
138 c = clk_get_rate(fpc->clk[index]); in fsl_pwm_calculate_period_clk()
156 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_period() argument
164 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS, in fsl_pwm_calculate_period()
169 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_calculate_period()
170 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_calculate_period()
180 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg); in fsl_pwm_calculate_period()
184 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); in fsl_pwm_calculate_period()
187 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_duty() argument
192 unsigned int period = fpc->period.mod_period + 1; in fsl_pwm_calculate_duty()
193 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); in fsl_pwm_calculate_duty()
201 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc, in fsl_pwm_is_any_pwm_enabled() argument
206 regmap_read(fpc->regmap, FTM_OUTMASK, &val); in fsl_pwm_is_any_pwm_enabled()
213 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc, in fsl_pwm_is_other_pwm_enabled() argument
218 regmap_read(fpc->regmap, FTM_OUTMASK, &val); in fsl_pwm_is_other_pwm_enabled()
225 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc, in fsl_pwm_apply_config() argument
235 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { in fsl_pwm_apply_config()
236 dev_err(fpc->chip.dev, "failed to calculate new period\n"); in fsl_pwm_apply_config()
240 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm)) in fsl_pwm_apply_config()
248 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) { in fsl_pwm_apply_config()
249 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) { in fsl_pwm_apply_config()
250 dev_err(fpc->chip.dev, in fsl_pwm_apply_config()
255 if (fpc->period.clk_select != periodcfg.clk_select) { in fsl_pwm_apply_config()
257 enum fsl_pwm_clk oldclk = fpc->period.clk_select; in fsl_pwm_apply_config()
260 ret = clk_prepare_enable(fpc->clk[newclk]); in fsl_pwm_apply_config()
263 clk_disable_unprepare(fpc->clk[oldclk]); in fsl_pwm_apply_config()
268 ftm_clear_write_protection(fpc); in fsl_pwm_apply_config()
271 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, in fsl_pwm_apply_config()
273 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, in fsl_pwm_apply_config()
275 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period); in fsl_pwm_apply_config()
277 fpc->period = periodcfg; in fsl_pwm_apply_config()
280 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle); in fsl_pwm_apply_config()
282 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), in fsl_pwm_apply_config()
284 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); in fsl_pwm_apply_config()
290 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); in fsl_pwm_apply_config()
292 ftm_set_write_protection(fpc); in fsl_pwm_apply_config()
300 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_apply() local
313 mutex_lock(&fpc->lock); in fsl_pwm_apply()
317 regmap_set_bits(fpc->regmap, FTM_OUTMASK, in fsl_pwm_apply()
319 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_apply()
320 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
326 ret = fsl_pwm_apply_config(fpc, pwm, newstate); in fsl_pwm_apply()
332 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
336 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_apply()
338 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
342 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm)); in fsl_pwm_apply()
346 mutex_unlock(&fpc->lock); in fsl_pwm_apply()
357 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) in fsl_pwm_init() argument
361 ret = clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_init()
365 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); in fsl_pwm_init()
366 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); in fsl_pwm_init()
367 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); in fsl_pwm_init()
369 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_init()
397 struct fsl_pwm_chip *fpc; in fsl_pwm_probe() local
401 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); in fsl_pwm_probe()
402 if (!fpc) in fsl_pwm_probe()
405 mutex_init(&fpc->lock); in fsl_pwm_probe()
407 fpc->soc = of_device_get_match_data(&pdev->dev); in fsl_pwm_probe()
408 fpc->chip.dev = &pdev->dev; in fsl_pwm_probe()
414 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, in fsl_pwm_probe()
416 if (IS_ERR(fpc->regmap)) { in fsl_pwm_probe()
418 return PTR_ERR(fpc->regmap); in fsl_pwm_probe()
421 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); in fsl_pwm_probe()
422 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { in fsl_pwm_probe()
424 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_probe()
427 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); in fsl_pwm_probe()
428 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) in fsl_pwm_probe()
429 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_probe()
431 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); in fsl_pwm_probe()
432 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) in fsl_pwm_probe()
433 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_probe()
435 fpc->clk[FSL_PWM_CLK_CNTEN] = in fsl_pwm_probe()
436 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); in fsl_pwm_probe()
437 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) in fsl_pwm_probe()
438 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_probe()
444 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in fsl_pwm_probe()
445 if (IS_ERR(fpc->ipg_clk)) in fsl_pwm_probe()
446 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; in fsl_pwm_probe()
449 fpc->chip.ops = &fsl_pwm_ops; in fsl_pwm_probe()
450 fpc->chip.npwm = 8; in fsl_pwm_probe()
452 ret = devm_pwmchip_add(&pdev->dev, &fpc->chip); in fsl_pwm_probe()
458 platform_set_drvdata(pdev, fpc); in fsl_pwm_probe()
460 return fsl_pwm_init(fpc); in fsl_pwm_probe()
466 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); in fsl_pwm_suspend() local
469 regcache_cache_only(fpc->regmap, true); in fsl_pwm_suspend()
470 regcache_mark_dirty(fpc->regmap); in fsl_pwm_suspend()
472 for (i = 0; i < fpc->chip.npwm; i++) { in fsl_pwm_suspend()
473 struct pwm_device *pwm = &fpc->chip.pwms[i]; in fsl_pwm_suspend()
478 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_suspend()
483 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_suspend()
484 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_suspend()
492 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); in fsl_pwm_resume() local
495 for (i = 0; i < fpc->chip.npwm; i++) { in fsl_pwm_resume()
496 struct pwm_device *pwm = &fpc->chip.pwms[i]; in fsl_pwm_resume()
501 clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_resume()
506 clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_resume()
507 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_resume()
511 regcache_cache_only(fpc->regmap, false); in fsl_pwm_resume()
512 regcache_sync(fpc->regmap); in fsl_pwm_resume()