Lines Matching refs:vreg
47 #define MT6332_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ argument
49 [MT6332_ID_##vreg] = { \
51 .name = #vreg, \
55 .id = MT6332_ID_##vreg, \
72 #define MT6332_LDO_LINEAR(match, vreg, min, max, step, volt_ranges, \ argument
75 [MT6332_ID_##vreg] = { \
77 .name = #vreg, \
81 .id = MT6332_ID_##vreg, \
100 #define MT6332_LDO_AO(match, vreg, ldo_volt_table, vosel, vosel_mask) \ argument
101 [MT6332_ID_##vreg] = { \
103 .name = #vreg, \
107 .id = MT6332_ID_##vreg, \
116 #define MT6332_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
118 [MT6332_ID_##vreg] = { \
120 .name = #vreg, \
124 .id = MT6332_ID_##vreg, \
139 #define MT6332_REG_FIXED(match, vreg, enreg, enbit, qibit, volt, stbit) \ argument
140 [MT6332_ID_##vreg] = { \
142 .name = #vreg, \
146 .id = MT6332_ID_##vreg, \