Lines Matching refs:REG_RTC_CTRL
20 #define REG_RTC_CTRL 0x00 macro
60 if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT)) in msc313_rtc_read_alarm()
71 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_alarm_irq_enable()
76 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_alarm_irq_enable()
96 return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT; in msc313_rtc_get_enabled()
103 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_enabled()
105 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_enabled()
117 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_read_time()
118 writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_read_time()
121 while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT) in msc313_rtc_read_time()
143 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_time()
144 writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_time()
147 while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT) in msc313_rtc_set_time()
170 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_interrupt()
173 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_interrupt()