Lines Matching refs:pm8001_cr32
402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); in pm8001_bar4_shift()
473 pm8001_cr32(pm8001_ha, 2, 0xd8); in mpi_set_phys_g3_with_ssc()
545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_init_check()
573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in check_fw_ready()
578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in check_fw_ready()
593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in check_fw_ready()
611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in check_fw_ready()
627 value = pm8001_cr32(pm8001_ha, 0, 0x44); in init_pci_device_addresses()
636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); in init_pci_device_addresses()
638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); in init_pci_device_addresses()
640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); in init_pci_device_addresses()
730 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_uninit_check()
772 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in soft_reset_ready_check()
792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & in soft_reset_ready_check()
795 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in soft_reset_ready_check()
796 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in soft_reset_ready_check()
801 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); in soft_reset_ready_check()
804 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); in soft_reset_ready_check()
843 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); in pm8001_chip_soft_rst()
854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); in pm8001_chip_soft_rst()
859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); in pm8001_chip_soft_rst()
869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); in pm8001_chip_soft_rst()
879 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in pm8001_chip_soft_rst()
897 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
900 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
914 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
918 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
925 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
928 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
935 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
938 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
944 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
955 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); in pm8001_chip_soft_rst()
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1007 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1008 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
1020 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1023 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1030 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1032 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1036 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1038 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
1042 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
1052 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1065 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm8001_chip_soft_rst()
1070 regVal = pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1076 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1080 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1084 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1098 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm8001_chip_soft_rst()
1103 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm8001_chip_soft_rst()
1110 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1114 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1134 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1142 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
4316 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); in pm8001_chip_is_our_interrupt()
4334 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); in pm8001_chip_isr()
4733 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()
4739 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()