Lines Matching refs:lw
44 lw s0, 0(t0)
45 lw s1, 4(t0)
46 lw s2, 8(t0)
47 lw s3, 12(t0)
48 lw s4, 16(t0)
49 lw s5, 20(t0)
80 lw zero, AON_CTRL_PM_CTRL(s0)
82 lw t0, AON_CTRL_PM_CTRL(s0)
104 1: lw t0, DDR40_PHY_CONTROL_REGS_0_PLL_STATUS(s1)
113 lw t0, TIMER_TIMER1_CTRL(s2)
117 lw t0, TIMER_TIMER1_CTRL(s2)
121 lw t1, TIMER_TIMER1_STAT(s2)
127 1: lw t0, TIMER_TIMER1_STAT(s2)
135 lw t1, AON_CTRL_HOST_MISC_CMDS(s0)
138 lw zero, AON_CTRL_PM_CTRL(s0)
174 lw s7, 32(sp)
175 lw s6, 28(sp)
176 lw s5, 24(sp)
177 lw s4, 20(sp)
178 lw s3, 16(sp)
179 lw s2, 12(sp)
180 lw s1, 8(sp)
181 lw s0, 4(sp)
182 lw ra, 0(sp)