Lines Matching refs:mas
105 struct spi_geni_master *mas, in get_spi_clk_cfg() argument
113 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
114 speed_hz * mas->oversampling, in get_spi_clk_cfg()
117 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
122 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
123 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
125 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
127 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
129 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
131 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
139 struct spi_geni_master *mas = spi_master_get_devdata(spi); in handle_se_timeout() local
141 struct geni_se *se = &mas->se; in handle_se_timeout()
144 spin_lock_irq(&mas->lock); in handle_se_timeout()
145 reinit_completion(&mas->cancel_done); in handle_se_timeout()
146 if (mas->cur_xfer_mode == GENI_SE_FIFO) in handle_se_timeout()
149 xfer = mas->cur_xfer; in handle_se_timeout()
150 mas->cur_xfer = NULL; in handle_se_timeout()
152 spin_unlock_irq(&mas->lock); in handle_se_timeout()
154 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_se_timeout()
158 spin_lock_irq(&mas->lock); in handle_se_timeout()
159 reinit_completion(&mas->abort_done); in handle_se_timeout()
161 spin_unlock_irq(&mas->lock); in handle_se_timeout()
163 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_se_timeout()
165 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_se_timeout()
171 mas->abort_failed = true; in handle_se_timeout()
175 if (mas->cur_xfer_mode == GENI_SE_DMA) { in handle_se_timeout()
177 if (xfer->tx_buf && mas->tx_se_dma) { in handle_se_timeout()
178 spin_lock_irq(&mas->lock); in handle_se_timeout()
179 reinit_completion(&mas->tx_reset_done); in handle_se_timeout()
181 spin_unlock_irq(&mas->lock); in handle_se_timeout()
182 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); in handle_se_timeout()
184 dev_err(mas->dev, "DMA TX RESET failed\n"); in handle_se_timeout()
185 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); in handle_se_timeout()
187 if (xfer->rx_buf && mas->rx_se_dma) { in handle_se_timeout()
188 spin_lock_irq(&mas->lock); in handle_se_timeout()
189 reinit_completion(&mas->rx_reset_done); in handle_se_timeout()
191 spin_unlock_irq(&mas->lock); in handle_se_timeout()
192 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); in handle_se_timeout()
194 dev_err(mas->dev, "DMA RX RESET failed\n"); in handle_se_timeout()
195 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in handle_se_timeout()
203 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); in handle_se_timeout()
210 struct spi_geni_master *mas = spi_master_get_devdata(spi); in handle_gpi_timeout() local
212 dmaengine_terminate_sync(mas->tx); in handle_gpi_timeout()
213 dmaengine_terminate_sync(mas->rx); in handle_gpi_timeout()
218 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_handle_err() local
220 switch (mas->cur_xfer_mode) { in spi_geni_handle_err()
229 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); in spi_geni_handle_err()
233 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) in spi_geni_is_abort_still_pending() argument
235 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending()
238 if (!mas->abort_failed) in spi_geni_is_abort_still_pending()
247 spin_lock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
250 spin_unlock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
253 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", in spi_geni_is_abort_still_pending()
262 mas->abort_failed = false; in spi_geni_is_abort_still_pending()
269 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in spi_geni_set_cs() local
270 struct spi_master *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs()
271 struct geni_se *se = &mas->se; in spi_geni_set_cs()
277 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
280 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
282 if (spi_geni_is_abort_still_pending(mas)) { in spi_geni_set_cs()
283 dev_err(mas->dev, "Can't set chip select\n"); in spi_geni_set_cs()
287 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
288 if (mas->cur_xfer) { in spi_geni_set_cs()
289 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); in spi_geni_set_cs()
290 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
294 mas->cs_flag = set_flag; in spi_geni_set_cs()
296 mas->cur_xfer_mode = GENI_SE_FIFO; in spi_geni_set_cs()
297 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
302 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
304 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
306 dev_warn(mas->dev, "Timeout setting chip select\n"); in spi_geni_set_cs()
311 pm_runtime_put(mas->dev); in spi_geni_set_cs()
314 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, in spi_setup_word_len() argument
319 struct geni_se *se = &mas->se; in spi_setup_word_len()
326 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
327 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
330 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
336 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, in geni_spi_set_clock_and_bw() argument
340 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw()
343 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
346 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); in geni_spi_set_clock_and_bw()
348 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
359 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
367 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
378 struct spi_geni_master *mas = spi_master_get_devdata(spi); in setup_fifo_params() local
379 struct geni_se *se = &mas->se; in setup_fifo_params()
383 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
397 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
399 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
406 mas->last_mode = spi_slv->mode; in setup_fifo_params()
409 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
434 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, in setup_gsi_xfer() argument
447 if (xfer->bits_per_word != mas->cur_bits_per_word || in setup_gsi_xfer()
448 xfer->speed_hz != mas->cur_speed_hz) { in setup_gsi_xfer()
449 mas->cur_bits_per_word = xfer->bits_per_word; in setup_gsi_xfer()
450 mas->cur_speed_hz = xfer->speed_hz; in setup_gsi_xfer()
460 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { in setup_gsi_xfer()
461 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); in setup_gsi_xfer()
463 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; in setup_gsi_xfer()
476 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, in setup_gsi_xfer()
479 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); in setup_gsi_xfer()
489 dmaengine_slave_config(mas->rx, &config); in setup_gsi_xfer()
490 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, in setup_gsi_xfer()
493 dev_err(mas->dev, "Err setting up rx desc\n"); in setup_gsi_xfer()
502 dmaengine_slave_config(mas->tx, &config); in setup_gsi_xfer()
503 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, in setup_gsi_xfer()
506 dev_err(mas->dev, "Err setting up tx desc\n"); in setup_gsi_xfer()
518 dma_async_issue_pending(mas->rx); in setup_gsi_xfer()
520 dma_async_issue_pending(mas->tx); in setup_gsi_xfer()
527 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in geni_can_dma() local
534 return mas->cur_xfer_mode == GENI_GPI_DMA; in geni_can_dma()
540 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_prepare_message() local
543 switch (mas->cur_xfer_mode) { in spi_geni_prepare_message()
546 if (spi_geni_is_abort_still_pending(mas)) in spi_geni_prepare_message()
550 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
558 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); in spi_geni_prepare_message()
562 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) in spi_geni_grab_gpi_chan() argument
566 mas->tx = dma_request_chan(mas->dev, "tx"); in spi_geni_grab_gpi_chan()
567 if (IS_ERR(mas->tx)) { in spi_geni_grab_gpi_chan()
568 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), in spi_geni_grab_gpi_chan()
573 mas->rx = dma_request_chan(mas->dev, "rx"); in spi_geni_grab_gpi_chan()
574 if (IS_ERR(mas->rx)) { in spi_geni_grab_gpi_chan()
575 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), in spi_geni_grab_gpi_chan()
583 mas->rx = NULL; in spi_geni_grab_gpi_chan()
584 dma_release_channel(mas->tx); in spi_geni_grab_gpi_chan()
586 mas->tx = NULL; in spi_geni_grab_gpi_chan()
590 static void spi_geni_release_dma_chan(struct spi_geni_master *mas) in spi_geni_release_dma_chan() argument
592 if (mas->rx) { in spi_geni_release_dma_chan()
593 dma_release_channel(mas->rx); in spi_geni_release_dma_chan()
594 mas->rx = NULL; in spi_geni_release_dma_chan()
597 if (mas->tx) { in spi_geni_release_dma_chan()
598 dma_release_channel(mas->tx); in spi_geni_release_dma_chan()
599 mas->tx = NULL; in spi_geni_release_dma_chan()
603 static int spi_geni_init(struct spi_geni_master *mas) in spi_geni_init() argument
605 struct geni_se *se = &mas->se; in spi_geni_init()
610 pm_runtime_get_sync(mas->dev); in spi_geni_init()
614 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
617 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
620 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
626 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
628 mas->tx_wm = 1; in spi_geni_init()
634 mas->oversampling = 2; in spi_geni_init()
636 mas->oversampling = 1; in spi_geni_init()
641 ret = spi_geni_grab_gpi_chan(mas); in spi_geni_init()
643 mas->cur_xfer_mode = GENI_GPI_DMA; in spi_geni_init()
645 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); in spi_geni_init()
652 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); in spi_geni_init()
656 mas->cur_xfer_mode = GENI_SE_FIFO; in spi_geni_init()
668 pm_runtime_put(mas->dev); in spi_geni_init()
672 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) in geni_byte_per_fifo_word() argument
679 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
680 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
683 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
686 static bool geni_spi_handle_tx(struct spi_geni_master *mas) in geni_spi_handle_tx() argument
688 struct geni_se *se = &mas->se; in geni_spi_handle_tx()
691 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); in geni_spi_handle_tx()
695 if (!mas->cur_xfer) { in geni_spi_handle_tx()
700 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
701 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
702 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
704 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
716 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
717 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
724 static void geni_spi_handle_rx(struct spi_geni_master *mas) in geni_spi_handle_rx() argument
726 struct geni_se *se = &mas->se; in geni_spi_handle_rx()
731 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); in geni_spi_handle_rx()
744 if (!mas->cur_xfer) { in geni_spi_handle_rx()
750 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
751 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
753 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
765 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
769 struct spi_geni_master *mas, in setup_se_xfer() argument
774 struct geni_se *se = &mas->se; in setup_se_xfer()
789 spin_lock_irq(&mas->lock); in setup_se_xfer()
790 spin_unlock_irq(&mas->lock); in setup_se_xfer()
792 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_se_xfer()
793 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_se_xfer()
794 mas->cur_bits_per_word = xfer->bits_per_word; in setup_se_xfer()
798 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_se_xfer()
802 mas->tx_rem_bytes = 0; in setup_se_xfer()
803 mas->rx_rem_bytes = 0; in setup_se_xfer()
805 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in setup_se_xfer()
806 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in setup_se_xfer()
808 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in setup_se_xfer()
811 mas->cur_xfer = xfer; in setup_se_xfer()
814 mas->tx_rem_bytes = xfer->len; in setup_se_xfer()
821 mas->rx_rem_bytes = xfer->len; in setup_se_xfer()
825 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; in setup_se_xfer()
826 mas->cur_xfer_mode = (len <= fifo_size) ? GENI_SE_FIFO : GENI_SE_DMA; in setup_se_xfer()
827 geni_se_select_mode(se, mas->cur_xfer_mode); in setup_se_xfer()
833 spin_lock_irq(&mas->lock); in setup_se_xfer()
836 if (mas->cur_xfer_mode == GENI_SE_DMA) { in setup_se_xfer()
839 xfer->len, &mas->rx_se_dma); in setup_se_xfer()
841 dev_err(mas->dev, "Failed to setup Rx dma %d\n", ret); in setup_se_xfer()
842 mas->rx_se_dma = 0; in setup_se_xfer()
848 xfer->len, &mas->tx_se_dma); in setup_se_xfer()
850 dev_err(mas->dev, "Failed to setup Tx dma %d\n", ret); in setup_se_xfer()
851 mas->tx_se_dma = 0; in setup_se_xfer()
854 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in setup_se_xfer()
855 mas->rx_se_dma = 0; in setup_se_xfer()
861 if (geni_spi_handle_tx(mas)) in setup_se_xfer()
862 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_se_xfer()
866 spin_unlock_irq(&mas->lock); in setup_se_xfer()
874 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_transfer_one() local
877 if (spi_geni_is_abort_still_pending(mas)) in spi_geni_transfer_one()
884 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { in spi_geni_transfer_one()
885 ret = setup_se_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
891 return setup_gsi_xfer(xfer, mas, slv, spi); in spi_geni_transfer_one()
897 struct spi_geni_master *mas = spi_master_get_devdata(spi); in geni_spi_isr() local
898 struct geni_se *se = &mas->se; in geni_spi_isr()
908 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
910 spin_lock(&mas->lock); in geni_spi_isr()
912 if (mas->cur_xfer_mode == GENI_SE_FIFO) { in geni_spi_isr()
914 geni_spi_handle_rx(mas); in geni_spi_isr()
917 geni_spi_handle_tx(mas); in geni_spi_isr()
920 if (mas->cur_xfer) { in geni_spi_isr()
922 mas->cur_xfer = NULL; in geni_spi_isr()
936 if (mas->tx_rem_bytes) { in geni_spi_isr()
938 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
939 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
941 if (mas->rx_rem_bytes) in geni_spi_isr()
942 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
943 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
945 complete(&mas->cs_done); in geni_spi_isr()
948 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { in geni_spi_isr()
949 const struct spi_transfer *xfer = mas->cur_xfer; in geni_spi_isr()
958 mas->tx_rem_bytes = 0; in geni_spi_isr()
960 mas->rx_rem_bytes = 0; in geni_spi_isr()
962 complete(&mas->tx_reset_done); in geni_spi_isr()
964 complete(&mas->rx_reset_done); in geni_spi_isr()
965 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { in geni_spi_isr()
966 if (xfer->tx_buf && mas->tx_se_dma) { in geni_spi_isr()
967 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); in geni_spi_isr()
968 mas->tx_se_dma = 0; in geni_spi_isr()
970 if (xfer->rx_buf && mas->rx_se_dma) { in geni_spi_isr()
971 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in geni_spi_isr()
972 mas->rx_se_dma = 0; in geni_spi_isr()
975 mas->cur_xfer = NULL; in geni_spi_isr()
980 complete(&mas->cancel_done); in geni_spi_isr()
982 complete(&mas->abort_done); in geni_spi_isr()
999 spin_unlock(&mas->lock); in geni_spi_isr()
1008 struct spi_geni_master *mas; in spi_geni_probe() local
1029 spi = devm_spi_alloc_master(dev, sizeof(*mas)); in spi_geni_probe()
1034 mas = spi_master_get_devdata(spi); in spi_geni_probe()
1035 mas->irq = irq; in spi_geni_probe()
1036 mas->dev = dev; in spi_geni_probe()
1037 mas->se.dev = dev; in spi_geni_probe()
1038 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
1039 mas->se.base = base; in spi_geni_probe()
1040 mas->se.clk = clk; in spi_geni_probe()
1066 init_completion(&mas->cs_done); in spi_geni_probe()
1067 init_completion(&mas->cancel_done); in spi_geni_probe()
1068 init_completion(&mas->abort_done); in spi_geni_probe()
1069 init_completion(&mas->tx_reset_done); in spi_geni_probe()
1070 init_completion(&mas->rx_reset_done); in spi_geni_probe()
1071 spin_lock_init(&mas->lock); in spi_geni_probe()
1076 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
1080 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
1081 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
1083 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
1087 ret = spi_geni_init(mas); in spi_geni_probe()
1096 if (mas->cur_xfer_mode == GENI_SE_FIFO) in spi_geni_probe()
1099 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
1109 free_irq(mas->irq, spi); in spi_geni_probe()
1111 spi_geni_release_dma_chan(mas); in spi_geni_probe()
1120 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_remove() local
1125 spi_geni_release_dma_chan(mas); in spi_geni_remove()
1127 free_irq(mas->irq, spi); in spi_geni_remove()
1135 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_runtime_suspend() local
1141 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
1145 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
1151 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_runtime_resume() local
1154 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
1158 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
1162 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()