Lines Matching refs:se
75 struct geni_se se; member
113 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
141 struct geni_se *se = &mas->se; in handle_se_timeout() local
147 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_se_timeout()
151 geni_se_cancel_m_cmd(se); in handle_se_timeout()
160 geni_se_abort_m_cmd(se); in handle_se_timeout()
180 writel(1, se->base + SE_DMA_TX_FSM_RST); in handle_se_timeout()
185 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); in handle_se_timeout()
190 writel(1, se->base + SE_DMA_RX_FSM_RST); in handle_se_timeout()
195 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in handle_se_timeout()
235 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending() local
248 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
249 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
271 struct geni_se *se = &mas->se; in spi_geni_set_cs() local
299 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); in spi_geni_set_cs()
301 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); in spi_geni_set_cs()
319 struct geni_se *se = &mas->se; in spi_setup_word_len() local
330 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
333 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
340 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw() local
363 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
364 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
367 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
368 ret = geni_icc_set_bw(se); in geni_spi_set_clock_and_bw()
379 struct geni_se *se = &mas->se; in setup_fifo_params() local
400 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
401 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
402 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
403 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
404 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
605 struct geni_se *se = &mas->se; in spi_geni_init() local
612 proto = geni_se_read_proto(se); in spi_geni_init()
617 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
620 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
626 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
629 ver = geni_se_get_qup_hw_version(se); in spi_geni_init()
638 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; in spi_geni_init()
644 geni_se_select_mode(se, GENI_GPI_DMA); in spi_geni_init()
657 geni_se_select_mode(se, GENI_SE_FIFO); in spi_geni_init()
663 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
665 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
688 struct geni_se *se = &mas->se; in geni_spi_handle_tx() local
696 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
714 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
718 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
726 struct geni_se *se = &mas->se; in geni_spi_handle_rx() local
734 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
746 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
761 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
774 struct geni_se *se = &mas->se; in setup_se_xfer() local
815 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_se_xfer()
820 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_se_xfer()
827 geni_se_select_mode(se, mas->cur_xfer_mode); in setup_se_xfer()
834 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); in setup_se_xfer()
838 ret = geni_se_rx_dma_prep(se, xfer->rx_buf, in setup_se_xfer()
847 ret = geni_se_tx_dma_prep(se, (void *)xfer->tx_buf, in setup_se_xfer()
854 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in setup_se_xfer()
862 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_se_xfer()
898 struct geni_se *se = &mas->se; in geni_spi_isr() local
901 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
937 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
950 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); in geni_spi_isr()
951 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); in geni_spi_isr()
954 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); in geni_spi_isr()
956 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); in geni_spi_isr()
967 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); in geni_spi_isr()
971 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); in geni_spi_isr()
997 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
1037 mas->se.dev = dev; in spi_geni_probe()
1038 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
1039 mas->se.base = base; in spi_geni_probe()
1040 mas->se.clk = clk; in spi_geni_probe()
1076 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
1080 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
1081 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
1083 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
1141 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
1145 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
1154 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
1158 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()