Lines Matching refs:regval
113 u32 regval; in pci1xxxx_spi_set_cs() local
116 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_set_cs()
118 regval &= ~SPI_MST_CTL_DEVSEL_MASK; in pci1xxxx_spi_set_cs()
119 regval |= (spi->chip_select << 25); in pci1xxxx_spi_set_cs()
120 writel(regval, in pci1xxxx_spi_set_cs()
123 regval &= ~(spi->chip_select << 25); in pci1xxxx_spi_set_cs()
124 writel(regval, in pci1xxxx_spi_set_cs()
163 u32 regval; in pci1xxxx_spi_transfer_one() local
172 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_one()
173 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_one()
192 regval = readl(par->reg_base + in pci1xxxx_spi_transfer_one()
194 regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK | in pci1xxxx_spi_transfer_one()
198 regval |= SPI_MST_CTL_MODE_SEL; in pci1xxxx_spi_transfer_one()
200 regval &= ~SPI_MST_CTL_MODE_SEL; in pci1xxxx_spi_transfer_one()
202 regval |= ((clkdiv << 5) | SPI_FORCE_CE | (len << 8)); in pci1xxxx_spi_transfer_one()
203 regval &= ~SPI_MST_CTL_CMD_LEN_MASK; in pci1xxxx_spi_transfer_one()
204 writel(regval, par->reg_base + in pci1xxxx_spi_transfer_one()
206 regval = readl(par->reg_base + in pci1xxxx_spi_transfer_one()
208 regval |= SPI_MST_CTL_GO; in pci1xxxx_spi_transfer_one()
209 writel(regval, par->reg_base + in pci1xxxx_spi_transfer_one()
226 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_one()
227 regval &= ~SPI_FORCE_CE; in pci1xxxx_spi_transfer_one()
228 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_one()
238 u32 regval; in pci1xxxx_spi_isr() local
241 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr()
242 if (regval & SPI_INTR) { in pci1xxxx_spi_isr()
248 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr()
260 u32 regval; in pci1xxxx_spi_probe() local
316 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
318 regval &= ~SPI_INTR; in pci1xxxx_spi_probe()
319 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
334 regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
336 regval |= (BIT(4)); in pci1xxxx_spi_probe()
338 regval &= ~(BIT(4)); in pci1xxxx_spi_probe()
340 writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
348 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
350 regval &= ~SPI_INTR; in pci1xxxx_spi_probe()
351 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
393 u32 regval; in store_restore_config() local
396 regval = readl(spi_ptr->reg_base + in store_restore_config()
398 regval &= SPI_MST_CTL_DEVSEL_MASK; in store_restore_config()
399 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7; in store_restore_config()
400 regval = readl(spi_ptr->reg_base + in store_restore_config()
402 regval &= SPI_MSI_VECTOR_SEL_MASK; in store_restore_config()
403 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1; in store_restore_config()
405 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); in store_restore_config()
406 regval &= ~SPI_MST_CTL_DEVSEL_MASK; in store_restore_config()
407 regval |= (spi_sub_ptr->prev_val.dev_sel << 25); in store_restore_config()
408 writel(regval, in store_restore_config()
419 u32 regval = SPI_RESUME_CONFIG; in pci1xxxx_spi_resume() local
425 writel(regval, spi_ptr->reg_base + in pci1xxxx_spi_resume()