Lines Matching refs:TB_CFG_SWITCH
1610 TB_CFG_SWITCH, 2, 2); in tb_switch_reset()
1640 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); in tb_switch_wait_for_bit()
1669 res = tb_sw_write(sw, ((u32 *) &sw->config) + 4, TB_CFG_SWITCH, 4, 1); in tb_plug_events_active()
1673 res = tb_sw_read(sw, &data, TB_CFG_SWITCH, sw->cap_plug_events + 1, 1); in tb_plug_events_active()
1696 return tb_sw_write(sw, &data, TB_CFG_SWITCH, in tb_plug_events_active()
2355 ret = tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5); in tb_switch_alloc()
2507 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH, in tb_switch_configure()
2524 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH, in tb_switch_configure()
3691 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, in tb_switch_mask_clx_objections()
3701 return tb_sw_write(sw, &val, TB_CFG_SWITCH, in tb_switch_mask_clx_objections()
3719 ret = tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()
3732 ret = tb_sw_write(sw, &command, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()
3741 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()