Lines Matching refs:UART010_CR
65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
99 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
110 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
313 port->membase + UART010_CR); in pl010_startup()
336 writel(0, port->membase + UART010_CR); in pl010_shutdown()
422 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE; in pl010_set_termios()
438 writel(old_cr, port->membase + UART010_CR); in pl010_set_termios()
555 old_cr = readb(port->membase + UART010_CR); in pl010_console_write()
556 writel(UART01x_CR_UARTEN, port->membase + UART010_CR); in pl010_console_write()
568 writel(old_cr, port->membase + UART010_CR); in pl010_console_write()
577 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { in pl010_console_get_options()