Lines Matching refs:UART_INTR
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) macro
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
229 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
231 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
242 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
244 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
400 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
402 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
445 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
743 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
746 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
756 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
757 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
833 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
854 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()