Lines Matching refs:R5
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
167 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
553 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
554 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
556 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
558 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
690 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
691 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
692 uap->curregs[R5] = new_reg; in pmz_break_ctl()
693 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
839 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
841 uap->curregs[R5] |= DTR; in __pmz_startup()
856 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
869 uap->curregs[R5] |= DTR; in pmz_irda_reset()
870 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
876 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
877 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
944 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
947 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
1142 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1143 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1192 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1193 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1903 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()