Lines Matching refs:cr3
48 .cr3 = 0x14,
65 .cr3 = 0x08,
87 .cr3 = 0x08,
181 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, in stm32_usart_config_reg_rs485() argument
188 *cr3 |= USART_CR3_DEM; in stm32_usart_config_reg_rs485()
224 u32 usartdiv, baud, cr1, cr3; in stm32_usart_config_rs485() local
237 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
247 stm32_usart_config_reg_rs485(&cr1, &cr3, in stm32_usart_config_rs485()
253 cr3 &= ~USART_CR3_DEP; in stm32_usart_config_rs485()
255 cr3 |= USART_CR3_DEP; in stm32_usart_config_rs485()
257 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
260 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
300 return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR); in stm32_usart_rx_dma_enabled()
469 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
475 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
480 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
514 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT); in stm32_usart_tx_dma_enabled()
524 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_tx_dma_complete()
543 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
576 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
596 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_pio()
623 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
677 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
705 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
720 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
778 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
822 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
824 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
858 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_stop_tx()
886 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_flush_buffer()
904 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_throttle()
908 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
924 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
931 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_unthrottle()
945 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_stop_rx()
949 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
994 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_start_rx_dma_cyclic()
1047 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1094 u32 cr1, cr2, cr3, isr; in stm32_usart_set_termios() local
1128 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1129 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; in stm32_usart_set_termios()
1132 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1134 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1192 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1200 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; in stm32_usart_set_termios()
1257 cr3 |= USART_CR3_EIE; in stm32_usart_set_termios()
1258 cr3 |= USART_CR3_DMAR; in stm32_usart_set_termios()
1259 cr3 |= USART_CR3_DDRE; in stm32_usart_set_termios()
1263 stm32_usart_config_reg_rs485(&cr1, &cr3, in stm32_usart_set_termios()
1268 cr3 &= ~USART_CR3_DEP; in stm32_usart_set_termios()
1271 cr3 |= USART_CR3_DEP; in stm32_usart_set_termios()
1276 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); in stm32_usart_set_termios()
1282 cr3 &= ~USART_CR3_WUS_MASK; in stm32_usart_set_termios()
1283 cr3 |= USART_CR3_WUS_START_BIT; in stm32_usart_set_termios()
1286 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1759 u32 cr3; in stm32_usart_serial_remove() local
1771 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1772 cr3 &= ~USART_CR3_EIE; in stm32_usart_serial_remove()
1773 cr3 &= ~USART_CR3_DMAR; in stm32_usart_serial_remove()
1774 cr3 &= ~USART_CR3_DDRE; in stm32_usart_serial_remove()
1775 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1787 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_serial_remove()
1971 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1982 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_serial_en_wakeup()
2001 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()