Lines Matching refs:BIT5
392 #define IRQ_DCD BIT5
2135 if (status & (BIT5 + BIT4)) { in isr_rdma()
2160 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4059 case 7: val |= BIT5; break; in async_mode()
4060 case 8: val |= BIT5 + BIT4; break; in async_mode()
4099 case 7: val |= BIT5; break; in async_mode()
4100 case 8: val |= BIT5 + BIT4; break; in async_mode()
4223 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4225 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4311 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4318 val |= BIT5; /* 001, txclk = RXC Input */ in sync_mode()
4396 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4401 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4463 val |= BIT5; /* 0010 */ in msc_set_vcr()
4466 val |= BIT7 + BIT6 + BIT5; /* 1110 */ in msc_set_vcr()
4872 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; in register_test()