Lines Matching refs:ep0_state
181 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_stall()
646 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_init()
799 && (udc->ep0_state == WAIT_FOR_SETUP)) { in ep0_setup_handle()
837 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_rx()
1104 if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP)) in qe_ep_tx()
1251 udc->ep0_state = DATA_STATE_NEED_ZLP; in ep0_prime_status()
1256 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()
1268 switch (udc->ep0_state) { in ep0_req_complete()
1278 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1290 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1310 ep->udc->ep0_state = WAIT_FOR_SETUP; in ep0_txcomplete()
1749 udc->ep0_state = DATA_STATE_XMIT; in __qe_ep_queue()
1751 udc->ep0_state = DATA_STATE_RECV; in __qe_ep_queue()
1841 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_set_halt()
2074 udc->ep0_state = DATA_STATE_XMIT; in setup_received_handle()
2077 udc->ep0_state = DATA_STATE_RECV; in setup_received_handle()
2093 udc->ep0_state = DATA_STATE_NEED_ZLP; in setup_received_handle()
2151 udc->ep0_state = WAIT_FOR_SETUP; in reset_irq()
2298 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_start()
2317 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_stop()