Lines Matching refs:vclk
426 u32 vclk; member
1367 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1371 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1374 if (vclk > c.ppll_max) in aty128_var_to_pll()
1375 vclk = c.ppll_max; in aty128_var_to_pll()
1376 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1377 vclk = c.ppll_min/12; in aty128_var_to_pll()
1381 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1396 pll->vclk = vclk; in aty128_var_to_pll()
1400 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
1410 var->pixclock = 100000000 / pll->vclk; in aty128_pll_to_var()
1440 d = pll->vclk * bpp; in aty128_ddafifo()