Lines Matching refs:INPLL
623 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { in radeon_probe_pll_params()
630 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); in radeon_probe_pll_params()
631 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); in radeon_probe_pll_params()
636 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); in radeon_probe_pll_params()
637 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); in radeon_probe_pll_params()
646 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); in radeon_probe_pll_params()
647 m = (INPLL(PPLL_REF_DIV) & 0x3ff); in radeon_probe_pll_params()
652 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { in radeon_probe_pll_params()
688 tmp = INPLL(M_SPLL_REF_FB_DIV); in radeon_probe_pll_params()
689 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
1121 tmp_pix_clks = INPLL(PIXCLKS_CNTL); in radeon_screen_blank()
1241 vclk_cntl = INPLL(VCLK_ECP_CNTL); in radeonfb_setcolreg()
1271 vclk_cntl = INPLL(VCLK_ECP_CNTL); in radeonfb_setcmap()
1337 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); in radeon_save_state()
1342 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1343 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1362 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1363 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1416 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()
1425 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) in radeon_write_pll_regs()