Lines Matching refs:INPLL
136 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
141 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
153 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
167 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
173 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
184 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
189 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
197 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
203 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
225 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
261 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
269 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_disable_dynamic_mode()
278 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
286 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
294 tmp = INPLL(pllMCLK_MISC); in radeon_pm_disable_dynamic_mode()
304 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
312 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
323 tmp = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
336 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
351 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
360 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
372 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
379 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
384 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
400 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
405 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
419 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
436 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
442 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
451 tmp = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
460 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_enable_dynamic_mode()
468 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
485 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
503 tmp = INPLL(pllPLL_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
509 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
520 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
528 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
536 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
563 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_save_regs()
564 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); in radeon_pm_save_regs()
565 rinfo->save_regs[2] = INPLL(MCLK_CNTL); in radeon_pm_save_regs()
566 rinfo->save_regs[3] = INPLL(SCLK_CNTL); in radeon_pm_save_regs()
567 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); in radeon_pm_save_regs()
568 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); in radeon_pm_save_regs()
569 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); in radeon_pm_save_regs()
570 rinfo->save_regs[7] = INPLL(MCLK_MISC); in radeon_pm_save_regs()
571 rinfo->save_regs[8] = INPLL(P2PLL_CNTL); in radeon_pm_save_regs()
599 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); in radeon_pm_save_regs()
610 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); in radeon_pm_save_regs()
611 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); in radeon_pm_save_regs()
612 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); in radeon_pm_save_regs()
613 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); in radeon_pm_save_regs()
614 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); in radeon_pm_save_regs()
660 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); in radeon_pm_save_regs()
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
662 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); in radeon_pm_save_regs()
663 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); in radeon_pm_save_regs()
664 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_save_regs()
665 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); in radeon_pm_save_regs()
676 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); in radeon_pm_save_regs()
677 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); in radeon_pm_save_regs()
678 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); in radeon_pm_save_regs()
682 rinfo->save_regs[97] = INPLL(pllMDLL_CKO); in radeon_pm_save_regs()
683 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); in radeon_pm_save_regs()
684 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); in radeon_pm_save_regs()
759 INPLL(pllP2PLL_REF_DIV); in radeon_pm_program_v2clk()
765 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP); in radeon_pm_program_v2clk()
768 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); in radeon_pm_program_v2clk()
772 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK) in radeon_pm_program_v2clk()
790 reg = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_low_current()
836 sclk_cntl = INPLL( pllSCLK_CNTL); in radeon_pm_setup_for_suspend()
873 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_setup_for_suspend()
881 mclk_cntl = INPLL( pllMCLK_CNTL); in radeon_pm_setup_for_suspend()
891 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_setup_for_suspend()
898 pixclks_cntl = INPLL( pllPIXCLKS_CNTL); in radeon_pm_setup_for_suspend()
914 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
924 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
946 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()
951 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; in radeon_pm_setup_for_suspend()
988 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; in radeon_pm_setup_for_suspend()
1031 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
1032 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ; in radeon_pm_setup_for_suspend()
1033 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()
1151 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP in radeon_pm_enable_dll()
1153 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP in radeon_pm_enable_dll()
1156 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP in radeon_pm_enable_dll()
1231 dll_value = INPLL(pllMDLL_RDCKA); in radeon_pm_enable_dll_m10()
1463 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_all_ppls_off()
1465 tmp = INPLL(pllP2PLL_CNTL); in radeon_pm_all_ppls_off()
1467 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1469 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_all_ppls_off()
1478 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1482 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1489 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1494 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1496 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1501 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1503 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1508 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1512 (void)INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1517 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1524 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1529 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1531 (void)INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1536 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1538 (void)INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1543 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1546 (void)INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1598 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1601 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1630 tmp = INPLL(pllSS_TST_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1644 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1648 tmp = INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1651 INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1656 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1667 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1671 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1675 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1679 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1814 tmp = INPLL(pllSCLK_CNTL); in radeon_reinitialize_M10()
1881 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ in radeon_reinitialize_M10()
1884 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_reinitialize_M10()
2156 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2161 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2179 tmp = INPLL(pllSSPLL_CNTL); in radeon_reinitialize_M9P()
2253 tmp = INPLL(pllVCLK_ECP_CNTL);
2255 tmp = INPLL(pllPIXCLKS_CNTL);
2270 tmp = INPLL(M_SPLL_REF_FB_DIV);
2272 tmp = INPLL(M_SPLL_REF_FB_DIV);
2274 INPLL(M_SPLL_REF_FB_DIV);
2276 tmp = INPLL(MPLL_CNTL);
2282 tmp = INPLL(M_SPLL_REF_FB_DIV);
2285 tmp = INPLL(MPLL_CNTL);
2288 tmp = INPLL(MPLL_CNTL);
2295 INPLL(M_SPLL_REF_FB_DIV);
2296 INPLL(MCLK_CNTL);
2297 INPLL(M_SPLL_REF_FB_DIV);
2299 tmp = INPLL(SPLL_CNTL);
2305 tmp = INPLL(M_SPLL_REF_FB_DIV);
2308 tmp = INPLL(SPLL_CNTL);
2311 tmp = INPLL(SPLL_CNTL);
2315 tmp = INPLL(SCLK_CNTL);
2319 cko = INPLL(pllMDLL_CKO);
2320 cka = INPLL(pllMDLL_RDCKA);
2321 ckb = INPLL(pllMDLL_RDCKB);
2390 tmp = INPLL(MCLK_MISC);
2394 tmp = INPLL(SCLK_CNTL);
2402 tmp = INPLL(VCLK_ECP_CNTL);
2405 tmp = INPLL(PPLL_CNTL);
2449 tmp = INPLL(PPLL_REF_DIV);
2452 INPLL(PPLL_REF_DIV);
2467 tmp = INPLL(PPLL_CNTL);
2470 tmp = INPLL(PPLL_CNTL);
2474 tmp = INPLL(VCLK_ECP_CNTL);
2478 tmp = INPLL(VCLK_ECP_CNTL);
2579 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET in radeon_set_suspend()
2719 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) || in radeon_check_power_loss()
2720 rinfo->save_regs[2] != INPLL(MCLK_CNTL) || in radeon_check_power_loss()
2721 rinfo->save_regs[3] != INPLL(SCLK_CNTL); in radeon_check_power_loss()