Lines Matching refs:par
96 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val) in i740outb() argument
98 vga_mm_w(par->regs, port, val); in i740outb()
100 static inline u8 i740inb(struct i740fb_par *par, u16 port) in i740inb() argument
102 return vga_mm_r(par->regs, port); in i740inb()
104 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) in i740outreg() argument
106 vga_mm_w_fast(par->regs, port, reg, val); in i740outreg()
108 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg) in i740inreg() argument
110 vga_mm_w(par->regs, port, reg); in i740inreg()
111 return vga_mm_r(par->regs, port+1); in i740inreg()
113 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, in i740outreg_mask() argument
116 vga_mm_w_fast(par->regs, port, reg, (val & mask) in i740outreg_mask()
117 | (i740inreg(par, port, reg) & ~mask)); in i740outreg_mask()
127 struct i740fb_par *par = data; in i740fb_ddc_setscl() local
129 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL); in i740fb_ddc_setscl()
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); in i740fb_ddc_setscl()
135 struct i740fb_par *par = data; in i740fb_ddc_setsda() local
137 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA); in i740fb_ddc_setsda()
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); in i740fb_ddc_setsda()
143 struct i740fb_par *par = data; in i740fb_ddc_getscl() local
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL); in i740fb_ddc_getscl()
147 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL); in i740fb_ddc_getscl()
152 struct i740fb_par *par = data; in i740fb_ddc_getsda() local
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA); in i740fb_ddc_getsda()
156 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA); in i740fb_ddc_getsda()
161 struct i740fb_par *par = info->par; in i740fb_setup_ddc_bus() local
163 strscpy(par->ddc_adapter.name, info->fix.id, in i740fb_setup_ddc_bus()
164 sizeof(par->ddc_adapter.name)); in i740fb_setup_ddc_bus()
165 par->ddc_adapter.owner = THIS_MODULE; in i740fb_setup_ddc_bus()
166 par->ddc_adapter.class = I2C_CLASS_DDC; in i740fb_setup_ddc_bus()
167 par->ddc_adapter.algo_data = &par->ddc_algo; in i740fb_setup_ddc_bus()
168 par->ddc_adapter.dev.parent = info->device; in i740fb_setup_ddc_bus()
169 par->ddc_algo.setsda = i740fb_ddc_setsda; in i740fb_setup_ddc_bus()
170 par->ddc_algo.setscl = i740fb_ddc_setscl; in i740fb_setup_ddc_bus()
171 par->ddc_algo.getsda = i740fb_ddc_getsda; in i740fb_setup_ddc_bus()
172 par->ddc_algo.getscl = i740fb_ddc_getscl; in i740fb_setup_ddc_bus()
173 par->ddc_algo.udelay = 10; in i740fb_setup_ddc_bus()
174 par->ddc_algo.timeout = 20; in i740fb_setup_ddc_bus()
175 par->ddc_algo.data = par; in i740fb_setup_ddc_bus()
177 i2c_set_adapdata(&par->ddc_adapter, par); in i740fb_setup_ddc_bus()
179 return i2c_bit_add_bus(&par->ddc_adapter); in i740fb_setup_ddc_bus()
184 struct i740fb_par *par = info->par; in i740fb_open() local
186 mutex_lock(&(par->open_lock)); in i740fb_open()
187 par->ref_count++; in i740fb_open()
188 mutex_unlock(&(par->open_lock)); in i740fb_open()
195 struct i740fb_par *par = info->par; in i740fb_release() local
197 mutex_lock(&(par->open_lock)); in i740fb_release()
198 if (par->ref_count == 0) { in i740fb_release()
200 mutex_unlock(&(par->open_lock)); in i740fb_release()
204 par->ref_count--; in i740fb_release()
205 mutex_unlock(&(par->open_lock)); in i740fb_release()
210 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp) in i740_calc_fifo() argument
235 if (par->has_sgram) { in i740_calc_fifo()
272 if (par->has_sgram) { in i740_calc_fifo()
307 if (par->has_sgram) { in i740_calc_fifo()
345 static void i740_calc_vclk(u32 freq, struct i740fb_par *par) in i740_calc_vclk() argument
386 par->video_clk2_m = (m_best - 2) & 0xFF; in i740_calc_vclk()
387 par->video_clk2_n = (n_best - 2) & 0xFF; in i740_calc_vclk()
388 par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS) in i740_calc_vclk()
390 par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1); in i740_calc_vclk()
394 struct i740fb_par *par, struct fb_info *info) in i740fb_decode_var() argument
444 dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD; in i740fb_decode_var()
502 par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5; in i740fb_decode_var()
503 par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1; in i740fb_decode_var()
504 par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1; in i740fb_decode_var()
505 par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3; in i740fb_decode_var()
506 par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F) in i740fb_decode_var()
508 par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F) in i740fb_decode_var()
511 par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2; in i740fb_decode_var()
519 par->crtc[VGA_CRTC_PRESET_ROW] = 0; in i740fb_decode_var()
520 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */ in i740fb_decode_var()
522 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80; in i740fb_decode_var()
523 par->crtc[VGA_CRTC_CURSOR_START] = 0x00; in i740fb_decode_var()
524 par->crtc[VGA_CRTC_CURSOR_END] = 0x00; in i740fb_decode_var()
525 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00; in i740fb_decode_var()
526 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00; in i740fb_decode_var()
527 par->crtc[VGA_CRTC_V_DISP_END] = yres-1; in i740fb_decode_var()
533 par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1; in i740fb_decode_var()
534 par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1; in i740fb_decode_var()
538 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; in i740fb_decode_var()
543 par->crtc[VGA_CRTC_V_SYNC_END] = in i740fb_decode_var()
546 par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF; in i740fb_decode_var()
548 par->crtc[VGA_CRTC_UNDERLINE] = 0x00; in i740fb_decode_var()
549 par->crtc[VGA_CRTC_MODE] = 0xC3 ; in i740fb_decode_var()
550 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF; in i740fb_decode_var()
551 par->crtc[VGA_CRTC_OVERFLOW] = r7; in i740fb_decode_var()
553 par->vss = 0x00; /* 3DA */ in i740fb_decode_var()
556 par->atc[i] = i; in i740fb_decode_var()
557 par->atc[VGA_ATC_MODE] = 0x81; in i740fb_decode_var()
558 par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */ in i740fb_decode_var()
559 par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F; in i740fb_decode_var()
560 par->atc[VGA_ATC_COLOR_PAGE] = 0x00; in i740fb_decode_var()
562 par->misc = 0xC3; in i740fb_decode_var()
564 par->misc &= ~0x40; in i740fb_decode_var()
566 par->misc &= ~0x80; in i740fb_decode_var()
568 par->seq[VGA_SEQ_CLOCK_MODE] = 0x01; in i740fb_decode_var()
569 par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F; in i740fb_decode_var()
570 par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00; in i740fb_decode_var()
571 par->seq[VGA_SEQ_MEMORY_MODE] = 0x06; in i740fb_decode_var()
573 par->gdc[VGA_GFX_SR_VALUE] = 0x00; in i740fb_decode_var()
574 par->gdc[VGA_GFX_SR_ENABLE] = 0x00; in i740fb_decode_var()
575 par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00; in i740fb_decode_var()
576 par->gdc[VGA_GFX_DATA_ROTATE] = 0x00; in i740fb_decode_var()
577 par->gdc[VGA_GFX_PLANE_READ] = 0; in i740fb_decode_var()
578 par->gdc[VGA_GFX_MODE] = 0x02; in i740fb_decode_var()
579 par->gdc[VGA_GFX_MISC] = 0x05; in i740fb_decode_var()
580 par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F; in i740fb_decode_var()
581 par->gdc[VGA_GFX_BIT_MASK] = 0xFF; in i740fb_decode_var()
586 par->crtc[VGA_CRTC_OFFSET] = vxres >> 3; in i740fb_decode_var()
587 par->ext_offset = vxres >> 11; in i740fb_decode_var()
588 par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE; in i740fb_decode_var()
589 par->bitblt_cntl = COLEXP_8BPP; in i740fb_decode_var()
593 par->pixelpipe_cfg1 = (var->green.length == 6) ? in i740fb_decode_var()
595 par->crtc[VGA_CRTC_OFFSET] = vxres >> 2; in i740fb_decode_var()
596 par->ext_offset = vxres >> 10; in i740fb_decode_var()
597 par->bitblt_cntl = COLEXP_16BPP; in i740fb_decode_var()
601 par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3; in i740fb_decode_var()
602 par->ext_offset = (vxres * 3) >> 11; in i740fb_decode_var()
603 par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE; in i740fb_decode_var()
604 par->bitblt_cntl = COLEXP_24BPP; in i740fb_decode_var()
609 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1; in i740fb_decode_var()
610 par->ext_offset = vxres >> 9; in i740fb_decode_var()
611 par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE; in i740fb_decode_var()
612 par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */ in i740fb_decode_var()
617 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_decode_var()
618 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_decode_var()
619 par->ext_start_addr = in i740fb_decode_var()
621 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_decode_var()
623 par->pixelpipe_cfg0 = DAC_8_BIT; in i740fb_decode_var()
625 par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE; in i740fb_decode_var()
626 par->io_cntl = EXTENDED_CRTC_CNTL; in i740fb_decode_var()
627 par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE; in i740fb_decode_var()
628 par->display_cntl = HIRES_MODE; in i740fb_decode_var()
631 par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */ in i740fb_decode_var()
634 par->ext_vert_total = (ytotal - 2) >> 8; in i740fb_decode_var()
635 par->ext_vert_disp_end = (yres - 1) >> 8; in i740fb_decode_var()
636 par->ext_vert_sync_start = (yres + lower) >> 8; in i740fb_decode_var()
637 par->ext_vert_blank_start = (yres + lower) >> 8; in i740fb_decode_var()
638 par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8; in i740fb_decode_var()
639 par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6; in i740fb_decode_var()
641 par->interlace_cntl = INTERLACE_DISABLE; in i740fb_decode_var()
644 par->atc[VGA_ATC_OVERSCAN] = 0; in i740fb_decode_var()
652 i740_calc_vclk(freq, par); in i740fb_decode_var()
655 par->misc |= 0x0C; in i740fb_decode_var()
658 par->lmi_fifo_watermark = in i740fb_decode_var()
659 i740_calc_fifo(par, 1000000 / var->pixclock, bpp); in i740fb_decode_var()
724 static void vga_protect(struct i740fb_par *par) in vga_protect() argument
727 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20); in vga_protect()
729 i740inb(par, 0x3DA); in vga_protect()
730 i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */ in vga_protect()
733 static void vga_unprotect(struct i740fb_par *par) in vga_unprotect() argument
736 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20); in vga_unprotect()
738 i740inb(par, 0x3DA); in vga_unprotect()
739 i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */ in vga_unprotect()
744 struct i740fb_par *par = info->par; in i740fb_set_par() local
748 i = i740fb_decode_var(&info->var, par, info); in i740fb_set_par()
754 vga_protect(par); in i740fb_set_par()
756 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE); in i740fb_set_par()
760 i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m); in i740fb_set_par()
761 i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n); in i740fb_set_par()
762 i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs); in i740fb_set_par()
763 i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel); in i740fb_set_par()
765 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, in i740fb_set_par()
766 par->pixelpipe_cfg0 & DAC_8_BIT, 0x80); in i740fb_set_par()
768 i740inb(par, 0x3DA); in i740fb_set_par()
769 i740outb(par, 0x3C0, 0x00); in i740fb_set_par()
772 i740outb(par, VGA_MIS_W, par->misc | 0x01); in i740fb_set_par()
775 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01); in i740fb_set_par()
777 i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, in i740fb_set_par()
778 par->seq[VGA_SEQ_CLOCK_MODE] | 0x20); in i740fb_set_par()
780 i740outreg(par, VGA_SEQ_I, i, par->seq[i]); in i740fb_set_par()
783 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03); in i740fb_set_par()
786 i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END, in i740fb_set_par()
787 par->crtc[VGA_CRTC_V_SYNC_END]); in i740fb_set_par()
791 i740outreg(par, VGA_CRT_IC, i, par->crtc[i]); in i740fb_set_par()
795 i740outreg(par, VGA_GFX_I, i, par->gdc[i]); in i740fb_set_par()
799 i740inb(par, VGA_IS1_RC); /* reset flip-flop */ in i740fb_set_par()
800 i740outb(par, VGA_ATT_IW, i); in i740fb_set_par()
801 i740outb(par, VGA_ATT_IW, par->atc[i]); in i740fb_set_par()
804 i740inb(par, VGA_IS1_RC); in i740fb_set_par()
805 i740outb(par, VGA_ATT_IW, 0x20); in i740fb_set_par()
807 i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total); in i740fb_set_par()
808 i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end); in i740fb_set_par()
809 i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START, in i740fb_set_par()
810 par->ext_vert_sync_start); in i740fb_set_par()
811 i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START, in i740fb_set_par()
812 par->ext_vert_blank_start); in i740fb_set_par()
813 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total); in i740fb_set_par()
814 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank); in i740fb_set_par()
815 i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset); in i740fb_set_par()
816 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi); in i740fb_set_par()
817 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr); in i740fb_set_par()
819 i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL, in i740fb_set_par()
820 par->interlace_cntl, INTERLACE_ENABLE); in i740fb_set_par()
821 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F); in i740fb_set_par()
822 i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE); in i740fb_set_par()
823 i740outreg_mask(par, XRX, DISPLAY_CNTL, in i740fb_set_par()
824 par->display_cntl, VGA_WRAP_MODE | GUI_MODE); in i740fb_set_par()
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B); in i740fb_set_par()
826 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C); in i740fb_set_par()
828 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl); in i740fb_set_par()
830 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1, in i740fb_set_par()
831 par->pixelpipe_cfg1, DISPLAY_COLOR_MODE); in i740fb_set_par()
833 itemp = readl(par->regs + FWATER_BLC); in i740fb_set_par()
835 itemp |= par->lmi_fifo_watermark; in i740fb_set_par()
836 writel(itemp, par->regs + FWATER_BLC); in i740fb_set_par()
838 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ); in i740fb_set_par()
840 i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY); in i740fb_set_par()
841 i740outreg_mask(par, XRX, IO_CTNL, in i740fb_set_par()
842 par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL); in i740fb_set_par()
844 if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) { in i740fb_set_par()
845 i740outb(par, VGA_PEL_MSK, 0xFF); in i740fb_set_par()
846 i740outb(par, VGA_PEL_IW, 0x00); in i740fb_set_par()
848 itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2; in i740fb_set_par()
849 i740outb(par, VGA_PEL_D, itemp); in i740fb_set_par()
850 i740outb(par, VGA_PEL_D, itemp); in i740fb_set_par()
851 i740outb(par, VGA_PEL_D, itemp); in i740fb_set_par()
857 vga_unprotect(par); in i740fb_set_par()
882 i740outb(info->par, VGA_PEL_IW, regno); in i740fb_setcolreg()
883 i740outb(info->par, VGA_PEL_D, red >> 8); in i740fb_setcolreg()
884 i740outb(info->par, VGA_PEL_D, green >> 8); in i740fb_setcolreg()
885 i740outb(info->par, VGA_PEL_D, blue >> 8); in i740fb_setcolreg()
908 struct i740fb_par *par = info->par; in i740fb_pan_display() local
935 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_pan_display()
936 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_pan_display()
937 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_pan_display()
938 par->ext_start_addr = in i740fb_pan_display()
941 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF); in i740fb_pan_display()
942 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI, in i740fb_pan_display()
944 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, in i740fb_pan_display()
946 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, in i740fb_pan_display()
954 struct i740fb_par *par = info->par; in i740fb_blank() local
981 i740outb(par, SRX, 0x01); in i740fb_blank()
982 SEQ01 |= i740inb(par, SRX + 1) & ~0x20; in i740fb_blank()
983 i740outb(par, SRX, 0x01); in i740fb_blank()
984 i740outb(par, SRX + 1, SEQ01); in i740fb_blank()
987 i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect); in i740fb_blank()
1012 struct i740fb_par *par; in i740fb_probe() local
1025 par = info->par; in i740fb_probe()
1026 mutex_init(&par->open_lock); in i740fb_probe()
1031 info->pseudo_palette = par->pseudo_palette; in i740fb_probe()
1052 par->regs = pci_ioremap_bar(dev, 1); in i740fb_probe()
1053 if (!par->regs) { in i740fb_probe()
1060 if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1) in i740fb_probe()
1062 i740outb(par, XRX, DRAM_ROW_BNDRY_1); in i740fb_probe()
1064 i740outb(par, XRX, DRAM_ROW_BNDRY_0); in i740fb_probe()
1065 info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024; in i740fb_probe()
1067 tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO); in i740fb_probe()
1068 par->has_sgram = !((tmp & DRAM_RAS_TIMING) || in i740fb_probe()
1073 par->has_sgram ? "SGRAM" : "SDRAM"); in i740fb_probe()
1083 par->ddc_registered = true; in i740fb_probe()
1084 edid = fb_ddc_read(&par->ddc_adapter); in i740fb_probe()
1150 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in i740fb_probe()
1158 if (par->ddc_registered) in i740fb_probe()
1159 i2c_del_adapter(&par->ddc_adapter); in i740fb_probe()
1160 pci_iounmap(dev, par->regs); in i740fb_probe()
1177 struct i740fb_par *par = info->par; in i740fb_remove() local
1178 arch_phys_wc_del(par->wc_cookie); in i740fb_remove()
1181 if (par->ddc_registered) in i740fb_remove()
1182 i2c_del_adapter(&par->ddc_adapter); in i740fb_remove()
1183 pci_iounmap(dev, par->regs); in i740fb_remove()
1194 struct i740fb_par *par = info->par; in i740fb_suspend() local
1197 mutex_lock(&(par->open_lock)); in i740fb_suspend()
1200 if (par->ref_count == 0) { in i740fb_suspend()
1201 mutex_unlock(&(par->open_lock)); in i740fb_suspend()
1208 mutex_unlock(&(par->open_lock)); in i740fb_suspend()
1217 struct i740fb_par *par = info->par; in i740fb_resume() local
1220 mutex_lock(&(par->open_lock)); in i740fb_resume()
1222 if (par->ref_count == 0) in i740fb_resume()
1229 mutex_unlock(&(par->open_lock)); in i740fb_resume()