Lines Matching refs:VIASR
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
45 via_write_reg(VIASR, 0x46, data & 0xFF); in cle266_set_primary_pll_encoded()
46 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF); in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
53 via_write_reg(VIASR, 0x44, data & 0xFF); in k800_set_primary_pll_encoded()
54 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); in k800_set_primary_pll_encoded()
55 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF); in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
61 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ in cle266_set_secondary_pll_encoded()
62 via_write_reg(VIASR, 0x44, data & 0xFF); in cle266_set_secondary_pll_encoded()
63 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); in cle266_set_secondary_pll_encoded()
64 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ in cle266_set_secondary_pll_encoded()
69 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ in k800_set_secondary_pll_encoded()
70 via_write_reg(VIASR, 0x4A, data & 0xFF); in k800_set_secondary_pll_encoded()
71 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF); in k800_set_secondary_pll_encoded()
72 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF); in k800_set_secondary_pll_encoded()
73 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ in k800_set_secondary_pll_encoded()
78 via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */ in set_engine_pll_encoded()
79 via_write_reg(VIASR, 0x47, data & 0xFF); in set_engine_pll_encoded()
80 via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF); in set_engine_pll_encoded()
81 via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF); in set_engine_pll_encoded()
82 via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */ in set_engine_pll_encoded()
140 via_write_reg_mask(VIASR, 0x2D, value, 0x30); in set_primary_pll_state()
158 via_write_reg_mask(VIASR, 0x2D, value, 0x0C); in set_secondary_pll_state()
176 via_write_reg_mask(VIASR, 0x2D, value, 0x03); in set_engine_pll_state()
194 via_write_reg_mask(VIASR, 0x1B, value, 0x30); in set_primary_clock_state()
212 via_write_reg_mask(VIASR, 0x1B, value, 0xC0); in set_secondary_clock_state()