Lines Matching refs:VIASR
11 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
12 {VIASR, SR15, 0x02, 0x02},
13 {VIASR, SR16, 0xBF, 0x08},
14 {VIASR, SR17, 0xFF, 0x1F},
15 {VIASR, SR18, 0xFF, 0x4E},
16 {VIASR, SR1A, 0xFB, 0x08},
17 {VIASR, SR1E, 0x0F, 0x01},
18 {VIASR, SR2A, 0xFF, 0x00},
44 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
45 {VIASR, SR15, 0x02, 0x02},
46 {VIASR, SR16, 0xBF, 0x08},
47 {VIASR, SR17, 0xFF, 0x1F},
48 {VIASR, SR18, 0xFF, 0x4E},
49 {VIASR, SR1A, 0xFB, 0x82},
50 {VIASR, SR1B, 0xFF, 0xF0},
51 {VIASR, SR1F, 0xFF, 0x00},
52 {VIASR, SR1E, 0xFF, 0x01},
53 {VIASR, SR22, 0xFF, 0x1F},
54 {VIASR, SR2A, 0x0F, 0x00},
55 {VIASR, SR2E, 0xFF, 0xFF},
56 {VIASR, SR3F, 0xFF, 0xFF},
57 {VIASR, SR40, 0xF7, 0x00},
58 {VIASR, CR30, 0xFF, 0x04},
94 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
95 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
96 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
97 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
98 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
99 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
100 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
101 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
102 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
103 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
104 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
105 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
106 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
107 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
131 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
132 {VIASR, SR15, 0x02, 0x02},
133 {VIASR, SR16, 0xBF, 0x08},
134 {VIASR, SR17, 0xFF, 0x1F},
135 {VIASR, SR18, 0xFF, 0x4E},
136 {VIASR, SR1A, 0xFB, 0x08},
137 {VIASR, SR1B, 0xFF, 0xF0},
138 {VIASR, SR1E, 0xFF, 0x01},
139 {VIASR, SR2A, 0xFF, 0x00},
140 {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
167 {VIASR, SR10, 0xFF, 0x01},
168 {VIASR, SR15, 0x02, 0x02},
169 {VIASR, SR16, 0xBF, 0x08},
170 {VIASR, SR17, 0xFF, 0x1F},
171 {VIASR, SR18, 0xFF, 0x4E},
172 {VIASR, SR1A, 0xFB, 0x08},
173 {VIASR, SR1B, 0xFF, 0xF0},
174 {VIASR, SR1E, 0x07, 0x01},
175 {VIASR, SR2A, 0xF0, 0x00},
176 {VIASR, SR58, 0xFF, 0x00},
177 {VIASR, SR59, 0xFF, 0x00},
178 {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
200 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
201 {VIASR, SR2A, 0x0F, 0x00},
202 {VIASR, SR15, 0x02, 0x02},
203 {VIASR, SR16, 0xBF, 0x08},
204 {VIASR, SR17, 0xFF, 0x1F},
205 {VIASR, SR18, 0xFF, 0x4E},
206 {VIASR, SR1A, 0xFB, 0x08},
224 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
225 {VIASR, 0x18, 0xFF, 0x4C}