Lines Matching defs:cap

1247 #define MLX5_CAP_GEN(mdev, cap) \  argument
1250 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1253 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1256 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1259 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1262 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1265 #define MLX5_CAP_ETH(mdev, cap) \  argument
1269 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1273 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1277 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1280 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1283 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1286 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1289 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1292 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1295 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1298 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1301 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1304 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1307 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1310 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1313 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1316 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1319 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1322 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1325 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1328 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1331 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1334 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1338 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1342 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1345 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1348 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1351 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1354 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1357 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1360 #define MLX5_CAP_ESW(mdev, cap) \  argument
1364 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1368 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1372 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1376 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1380 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1384 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \  argument
1388 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1391 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \  argument
1394 #define MLX5_CAP_ODP(mdev, cap)\  argument
1397 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1400 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1404 #define MLX5_CAP_QOS(mdev, cap)\  argument
1407 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1437 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1440 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1443 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1446 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1449 #define MLX5_CAP_TLS(mdev, cap) \  argument
1452 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1455 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1459 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1463 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1466 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1469 #define MLX5_CAP_DEV_SHAMPO(mdev, cap)\  argument
1472 #define MLX5_CAP_MACSEC(mdev, cap)\  argument