Lines Matching refs:cap
1247 #define MLX5_CAP_GEN(mdev, cap) \ argument
1248 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1250 #define MLX5_CAP_GEN_64(mdev, cap) \ argument
1251 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1253 #define MLX5_CAP_GEN_MAX(mdev, cap) \ argument
1254 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1256 #define MLX5_CAP_GEN_2(mdev, cap) \ argument
1257 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1259 #define MLX5_CAP_GEN_2_64(mdev, cap) \ argument
1260 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1262 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ argument
1263 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1265 #define MLX5_CAP_ETH(mdev, cap) \ argument
1267 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1269 #define MLX5_CAP_ETH_MAX(mdev, cap) \ argument
1271 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap)
1273 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ argument
1275 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1277 #define MLX5_CAP_ROCE(mdev, cap) \ argument
1278 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1280 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ argument
1281 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1283 #define MLX5_CAP_ATOMIC(mdev, cap) \ argument
1284 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1286 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ argument
1287 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1289 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ argument
1290 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1292 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ argument
1293 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1295 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ argument
1296 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap)
1298 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ argument
1299 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1301 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ argument
1302 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1304 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ argument
1305 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1307 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ argument
1308 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1310 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ argument
1311 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1313 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ argument
1314 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1316 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ argument
1317 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1319 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ argument
1320 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1322 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ argument
1323 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1325 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ argument
1326 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1328 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ argument
1329 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1331 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ argument
1332 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1334 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ argument
1336 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1338 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ argument
1340 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap)
1342 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ argument
1343 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1345 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ argument
1346 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1348 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ argument
1349 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1351 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ argument
1352 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1354 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ argument
1355 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1357 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ argument
1358 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1360 #define MLX5_CAP_ESW(mdev, cap) \ argument
1362 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1364 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ argument
1366 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1368 #define MLX5_CAP_ESW_MAX(mdev, cap) \ argument
1370 mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap)
1372 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ argument
1374 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1376 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ argument
1378 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1380 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ argument
1382 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1384 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \ argument
1386 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap)
1388 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ argument
1389 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1391 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \ argument
1392 MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap)
1394 #define MLX5_CAP_ODP(mdev, cap)\ argument
1395 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1397 #define MLX5_CAP_ODP_MAX(mdev, cap)\ argument
1398 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1400 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ argument
1402 mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap)
1404 #define MLX5_CAP_QOS(mdev, cap)\ argument
1405 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1407 #define MLX5_CAP_DEBUG(mdev, cap)\ argument
1408 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1437 #define MLX5_CAP_FPGA(mdev, cap) \ argument
1438 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1440 #define MLX5_CAP64_FPGA(mdev, cap) \ argument
1441 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1443 #define MLX5_CAP_DEV_MEM(mdev, cap)\ argument
1444 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1446 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ argument
1447 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1449 #define MLX5_CAP_TLS(mdev, cap) \ argument
1450 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1452 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ argument
1453 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1455 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ argument
1457 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1459 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ argument
1461 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1463 #define MLX5_CAP_IPSEC(mdev, cap)\ argument
1464 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1466 #define MLX5_CAP_CRYPTO(mdev, cap)\ argument
1467 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1469 #define MLX5_CAP_DEV_SHAMPO(mdev, cap)\ argument
1470 MLX5_GET(shampo_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_SHAMPO], cap)
1472 #define MLX5_CAP_MACSEC(mdev, cap)\ argument
1473 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)