Lines Matching defs:drm_amdgpu_info_device
1033 struct drm_amdgpu_info_device { struct
1035 __u32 device_id;
1037 __u32 chip_rev;
1038 __u32 external_rev;
1040 __u32 pci_rev;
1041 __u32 family;
1042 __u32 num_shader_engines;
1043 __u32 num_shader_arrays_per_engine;
1045 __u32 gpu_counter_freq;
1046 __u64 max_engine_clock;
1047 __u64 max_memory_clock;
1049 __u32 cu_active_number;
1051 __u32 cu_ao_mask;
1052 __u32 cu_bitmap[4][4];
1054 __u32 enabled_rb_pipes_mask;
1055 __u32 num_rb_pipes;
1056 __u32 num_hw_gfx_contexts;
1058 __u32 pcie_gen;
1059 __u64 ids_flags;
1061 __u64 virtual_address_offset;
1063 __u64 virtual_address_max;
1065 __u32 virtual_address_alignment;
1067 __u32 pte_fragment_size;
1068 __u32 gart_page_size;
1070 __u32 ce_ram_size;
1072 __u32 vram_type;
1074 __u32 vram_bit_width;
1076 __u32 vce_harvest_config;
1078 __u32 gc_double_offchip_lds_buf;
1080 __u64 prim_buf_gpu_addr;
1082 __u64 pos_buf_gpu_addr;
1084 __u64 cntl_sb_buf_gpu_addr;
1086 __u64 param_buf_gpu_addr;
1087 __u32 prim_buf_size;
1088 __u32 pos_buf_size;
1089 __u32 cntl_sb_buf_size;
1090 __u32 param_buf_size;
1092 __u32 wave_front_size;
1094 __u32 num_shader_visible_vgprs;
1096 __u32 num_cu_per_sh;
1098 __u32 num_tcc_blocks;
1100 __u32 gs_vgt_table_depth;
1102 __u32 gs_prim_buffer_depth;
1104 __u32 max_gs_waves_per_vgt;
1106 __u32 pcie_num_lanes;
1108 __u32 cu_ao_bitmap[4][4];
1110 __u64 high_va_offset;
1112 __u64 high_va_max;
1114 __u32 pa_sc_tile_steering_override;
1116 __u64 tcc_disabled_mask;
1117 __u64 min_engine_clock;
1118 __u64 min_memory_clock;
1120 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */
1121 __u32 num_sqc_per_wgp;
1122 __u32 sqc_data_cache_size; /* AKA SMEM cache */
1123 __u32 sqc_inst_cache_size;
1124 __u32 gl1c_cache_size;
1125 __u32 gl2c_cache_size;
1126 __u64 mall_size; /* AKA infinity cache */
1128 __u32 enabled_rb_pipes_mask_hi;