Lines Matching refs:V4L2_INIT_BT_TIMINGS
16 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
19 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
27 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
37 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
47 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
58 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
68 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
77 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
105 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
114 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
134 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
143 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
153 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
163 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
172 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
183 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
193 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
204 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
214 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
225 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
234 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
244 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
255 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
264 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
274 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
283 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
296 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
303 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
310 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
320 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
327 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
334 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
342 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
350 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
358 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
366 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
374 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
382 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
390 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
398 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
407 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
414 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
421 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
429 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
437 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
446 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
457 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
472 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
479 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
486 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
494 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
509 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
516 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
523 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
531 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
539 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
547 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
556 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
564 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
572 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
580 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
588 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
596 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
604 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
612 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
621 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
636 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
643 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
650 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
659 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
674 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
681 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
688 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
696 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
705 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
713 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
721 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
729 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
737 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
745 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
754 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
769 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
776 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
783 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
791 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
798 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
805 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
813 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
820 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
827 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
838 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
853 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
860 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
867 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
875 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
882 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
889 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
897 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
906 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
921 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
928 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
935 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
944 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
952 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
963 V4L2_INIT_BT_TIMINGS(720, 487, 1, \