Lines Matching refs:OPTi9XX_MC_REG
99 #define OPTi9XX_MC_REG(n) n macro
337 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0xf0, 0xfc); in snd_opti9xx_configure()
339 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02); in snd_opti9xx_configure()
344 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80); in snd_opti9xx_configure()
346 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20); in snd_opti9xx_configure()
348 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff); in snd_opti9xx_configure()
351 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02); in snd_opti9xx_configure()
354 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02); in snd_opti9xx_configure()
360 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80); in snd_opti9xx_configure()
361 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20); in snd_opti9xx_configure()
365 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c); in snd_opti9xx_configure()
367 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02); in snd_opti9xx_configure()
369 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02); in snd_opti9xx_configure()
376 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(20), 0x04, 0x0c); in snd_opti9xx_configure()
384 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(21), 0x82, 0xff); in snd_opti9xx_configure()
389 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(26), 0x01, 0x01); in snd_opti9xx_configure()
393 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x03); in snd_opti9xx_configure()
394 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0x00, 0xff); in snd_opti9xx_configure()
395 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x10 | in snd_opti9xx_configure()
398 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x20, 0xbf); in snd_opti9xx_configure()
429 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30); in snd_opti9xx_configure()
490 snd_opti9xx_write(chip, OPTi9XX_MC_REG(3), (irq_bits << 3 | dma_bits)); in snd_opti9xx_configure()
536 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), in snd_opti9xx_configure()
644 status = snd_opti9xx_read(chip, OPTi9XX_MC_REG(11)); in snd_opti93x_interrupt()
671 value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(1)); in snd_opti9xx_read_check()
672 if (value != 0xff && value != inb(chip->mc_base + OPTi9XX_MC_REG(1))) in snd_opti9xx_read_check()
673 if (value == snd_opti9xx_read(chip, OPTi9XX_MC_REG(1))) in snd_opti9xx_read_check()
687 value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(7)); in snd_opti9xx_read_check()
688 snd_opti9xx_write(chip, OPTi9XX_MC_REG(7), 0xff - value); in snd_opti9xx_read_check()
689 if (snd_opti9xx_read(chip, OPTi9XX_MC_REG(7)) == 0xff - value) in snd_opti9xx_read_check()
891 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
896 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),