Lines Matching refs:control_reg
162 u32 control_reg, clock, base_rate; in set_sample_rate() local
179 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
180 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
197 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
222 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
240 control_reg |= clock; in set_sample_rate()
245 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate()
247 return write_control_reg(chip, control_reg, false); in set_sample_rate()
254 u32 control_reg, clocks_from_dsp; in set_input_clock() local
257 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
269 control_reg |= GML_SPDIF_CLOCK; in set_input_clock()
271 control_reg &= ~GML_DOUBLE_SPEED_MODE; in set_input_clock()
274 control_reg |= GML_WORD_CLOCK; in set_input_clock()
276 control_reg |= GML_DOUBLE_SPEED_MODE; in set_input_clock()
278 control_reg &= ~GML_DOUBLE_SPEED_MODE; in set_input_clock()
283 control_reg |= GML_ADAT_CLOCK; in set_input_clock()
284 control_reg &= ~GML_DOUBLE_SPEED_MODE; in set_input_clock()
293 return write_control_reg(chip, control_reg, true); in set_input_clock()
335 u32 control_reg; in dsp_set_digital_mode() local
373 control_reg = le32_to_cpu(chip->comm_page->control_register); in dsp_set_digital_mode()
374 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; in dsp_set_digital_mode()
378 control_reg |= GML_SPDIF_OPTICAL_MODE; in dsp_set_digital_mode()
384 control_reg |= GML_ADAT_MODE; in dsp_set_digital_mode()
385 control_reg &= ~GML_DOUBLE_SPEED_MODE; in dsp_set_digital_mode()
389 err = write_control_reg(chip, control_reg, true); in dsp_set_digital_mode()