Lines Matching refs:clk_set_parent
69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
231 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8192_afe_enable_clock()
255 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], in mt8192_afe_enable_clock()
584 ret = clk_set_parent(afe_priv->clk[m_sel_id], in mt8192_mck_enable()