Lines Matching refs:snd_sof_dsp_write
48 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr); in init_dma_descriptor()
49 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT); in init_dma_descriptor()
62 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); in configure_dma_descriptor()
63 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); in configure_dma_descriptor()
64 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); in configure_dma_descriptor()
74 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), in config_dma_channel()
88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0); in config_dma_channel()
89 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count); in config_dma_channel()
90 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx); in config_dma_channel()
91 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0); in config_dma_channel()
92 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); in config_dma_channel()
230 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); in configure_and_run_sha_dma()
241 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); in configure_and_run_sha_dma()
242 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); in configure_and_run_sha_dma()
243 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); in configure_and_run_sha_dma()
244 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); in configure_and_run_sha_dma()
302 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); in memcpy_to_scratch()
326 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, val); in acp_irq_thread()
341 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); in acp_irq_thread()
356 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, val); in acp_irq_handler()
376 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, in acp_power_on()
393 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); in acp_reset()
403 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); in acp_reset()
410 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); in acp_reset()
425 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); in acp_init()
440 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00); in amd_sof_acp_suspend()
457 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); in amd_sof_acp_resume()