Lines Matching refs:sdev
29 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset) in hda_dsp_ctrl_link_reset() argument
39 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL, in hda_dsp_ctrl_link_reset()
45 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); in hda_dsp_ctrl_link_reset()
52 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n", in hda_dsp_ctrl_link_reset()
57 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev) in hda_dsp_ctrl_get_caps() argument
59 struct hdac_bus *bus = sof_to_bus(sdev); in hda_dsp_ctrl_get_caps()
68 ret = hda_dsp_ctrl_link_reset(sdev, true); in hda_dsp_ctrl_get_caps()
71 ret = hda_dsp_ctrl_link_reset(sdev, false); in hda_dsp_ctrl_get_caps()
75 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH); in hda_dsp_ctrl_get_caps()
78 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n", in hda_dsp_ctrl_get_caps()
81 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset); in hda_dsp_ctrl_get_caps()
92 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n", in hda_dsp_ctrl_get_caps()
95 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap; in hda_dsp_ctrl_get_caps()
98 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n", in hda_dsp_ctrl_get_caps()
101 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap; in hda_dsp_ctrl_get_caps()
104 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n", in hda_dsp_ctrl_get_caps()
107 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap; in hda_dsp_ctrl_get_caps()
110 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n", in hda_dsp_ctrl_get_caps()
115 dev_dbg(sdev->dev, "found ML capability at 0x%x\n", in hda_dsp_ctrl_get_caps()
120 dev_dbg(sdev->dev, "found capability %d at 0x%x\n", in hda_dsp_ctrl_get_caps()
131 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable) in hda_dsp_ctrl_ppcap_enable() argument
135 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, in hda_dsp_ctrl_ppcap_enable()
139 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable) in hda_dsp_ctrl_ppcap_int_enable() argument
143 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, in hda_dsp_ctrl_ppcap_int_enable()
147 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable) in hda_dsp_ctrl_misc_clock_gating() argument
151 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val); in hda_dsp_ctrl_misc_clock_gating()
159 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable) in hda_dsp_ctrl_clock_power_gating() argument
165 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val); in hda_dsp_ctrl_clock_power_gating()
169 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, in hda_dsp_ctrl_clock_power_gating()
174 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val); in hda_dsp_ctrl_clock_power_gating()
179 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev) in hda_dsp_ctrl_init_chip() argument
181 struct hdac_bus *bus = sof_to_bus(sdev); in hda_dsp_ctrl_init_chip()
188 hda_codec_set_codec_wakeup(sdev, true); in hda_dsp_ctrl_init_chip()
190 hda_dsp_ctrl_misc_clock_gating(sdev, false); in hda_dsp_ctrl_init_chip()
193 ret = hda_dsp_ctrl_link_reset(sdev, true); in hda_dsp_ctrl_init_chip()
195 dev_err(sdev->dev, "error: failed to reset HDA controller\n"); in hda_dsp_ctrl_init_chip()
200 ret = hda_dsp_ctrl_link_reset(sdev, false); in hda_dsp_ctrl_init_chip()
202 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n"); in hda_dsp_ctrl_init_chip()
206 hda_codec_detect_mask(sdev); in hda_dsp_ctrl_init_chip()
211 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_init_chip()
217 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_init_chip()
220 hda_codec_rirb_status_clear(sdev); in hda_dsp_ctrl_init_chip()
223 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_init_chip()
226 hda_codec_init_cmd_io(sdev); in hda_dsp_ctrl_init_chip()
229 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_init_chip()
235 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, in hda_dsp_ctrl_init_chip()
237 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, in hda_dsp_ctrl_init_chip()
246 hda_dsp_ctrl_misc_clock_gating(sdev, true); in hda_dsp_ctrl_init_chip()
248 hda_codec_set_codec_wakeup(sdev, false); in hda_dsp_ctrl_init_chip()
253 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev) in hda_dsp_ctrl_stop_chip() argument
255 struct hdac_bus *bus = sof_to_bus(sdev); in hda_dsp_ctrl_stop_chip()
265 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
273 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
277 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
284 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
290 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_stop_chip()
293 hda_codec_rirb_status_clear(sdev); in hda_dsp_ctrl_stop_chip()
296 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_stop_chip()
299 hda_codec_stop_cmd_io(sdev); in hda_dsp_ctrl_stop_chip()
303 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
305 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()