Lines Matching refs:EBX
15 1, 0, EBX, 7:0, brand, Brand Index
16 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
17 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
18 1, 0, EBX, 31:24, apic_id, Initial APIC ID
100 4, 0, EBX, 11:0, cache_linesize, Size of a cache line in bytes
101 4, 0, EBX, 21:12, cache_partition, Physical Line partitions
102 4, 0, EBX, 31:22, cache_ways, Ways of associativity
111 5, 0, EBX, 15:0, max_mon_size, Largest monitor line size in bytes
148 6, 0, EBX, 3:0, therm_irq_thresh, Number of Interrupt Thresholds in Digital Thermal Sensor
157 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported
158 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported
159 7, 0, EBX, 2, sgx, Software Guard Extensions
160 7, 0, EBX, 3, bmi1, BMI1
161 7, 0, EBX, 4, hle, Hardware Lock Elision
162 7, 0, EBX, 5, avx2, AVX2
163 # 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions
164 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention
165 7, 0, EBX, 8, bmi2, BMI2
166 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB
167 7, 0, EBX, 10, invpcid, INVPCID instruction
168 7, 0, EBX, 11, rtm, Restricted Transactional Memory
169 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability
170 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS
171 7, 0, EBX, 14, mpx, Memory Protection Extensions
172 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability
173 7, 0, EBX, 16, avx512f, AVX512 Foundation instr
174 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr
175 7, 0, EBX, 18, rdseed, RDSEED instr
176 7, 0, EBX, 19, adx, ADX instr
177 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention
178 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add
179 # 7, 0, EBX, 22, resvd, resvd
180 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr
181 7, 0, EBX, 24, clwb, CLWB instr
182 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr
183 7, 0, EBX, 26, avx512pf, Prefetch
184 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
185 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
186 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
187 7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr
188 7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL)
219 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events
221 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not available
222 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired event not available
223 0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles event not available
224 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache reference event not available
225 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses event not available
226 … 0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instruction retired event not available
227 … 0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredict retired event not available
237 0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at this level type
252 … 0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
260 … 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
270 …0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RMID within this physical proce…
281 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported
282 0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation supported
283 0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation supported
303 0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/”core crystal clock” ratio
310 0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz
317 0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID
318 0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an industry standard scheme
380 0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD
385 # EBX: Core Identifiers
386 0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID
387 0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per core is threads_per_core + 1
397 0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memory encryption
398 0x8000001F, 0, EBX, 11:6, mem_encrypt_physaddr_width, Reduction of physical address space in bits…