Lines Matching refs:HWREG
113 while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) in HibernateWriteComplete()
147 HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; in HibernateEnableExpClk()
186 HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; in HibernateDisable()
231 HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL); in HibernateClockSelect()
281 ulHIBCtl = HWREG(HIB_CTL); in HibernateClockConfig()
298 HWREG(HIB_CTL) = ulHIBCtl; in HibernateClockConfig()
324 HWREG(HIB_CTL) |= HIB_CTL_RTCEN; in HibernateRTCEnable()
349 HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; in HibernateRTCDisable()
383 HWREG(HIB_CTL) |= HIB_CTL_BATCHK; in HibernateBatCheckStart()
415 return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); in HibernateBatCheckDone()
451 HWREG(HIB_CTL) = (ulWakeFlags | in HibernateWakeSet()
452 (HWREG(HIB_CTL) & ~(HIBERNATE_WAKE_PIN | in HibernateWakeSet()
489 return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | in HibernateWakeGet()
543 HWREG(HIB_CTL) = (ulLowBatFlags | in HibernateLowBatSet()
544 (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M in HibernateLowBatSet()
573 return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); in HibernateLowBatGet()
595 HWREG(HIB_RTCLD) = ulRTCValue; in HibernateRTCSet()
618 return(HWREG(HIB_RTCC)); in HibernateRTCGet()
641 HWREG(HIB_RTCM0) = ulMatch; in HibernateRTCMatch0Set()
664 return(HWREG(HIB_RTCM0)); in HibernateRTCMatch0Get()
691 HWREG(HIB_RTCM1) = ulMatch; in HibernateRTCMatch1Set()
718 return(HWREG(HIB_RTCM1)); in HibernateRTCMatch1Get()
746 HWREG(HIB_RTCSS) = ulMatch << HIB_RTCSS_RTCSSM_S; in HibernateRTCSSMatch0Set()
774 return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); in HibernateRTCSSMatch0Get()
797 return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); in HibernateRTCSSGet()
829 HWREG(HIB_RTCT) = ulTrim; in HibernateRTCTrimSet()
854 return(HWREG(HIB_RTCT)); in HibernateRTCTrimGet()
899 HWREG(HIB_DATA + (ulIdx * 4)) = pulData[ulIdx]; in HibernateDataSet()
951 pulData[ulIdx] = HWREG(HIB_DATA + (ulIdx * 4)); in HibernateDataGet()
996 HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; in HibernateRequest()
1044 HWREG(HIB_IM) |= ulIntFlags; in HibernateIntEnable()
1081 HWREG(HIB_IM) &= ~ulIntFlags; in HibernateIntDisable()
1172 return(HWREG(HIB_MIS) & 0x1f); in HibernateIntStatus()
1176 return(HWREG(HIB_RIS) & 0x1f); in HibernateIntStatus()
1219 HWREG(HIB_IC) |= ulIntFlags; in HibernateIntClear()
1254 return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); in HibernateIsActive()
1282 HWREG(HIB_CTL) |= HIB_CTL_VDD3ON; in HibernateGPIORetentionEnable()
1313 HWREG(HIB_CTL) &= ~HIB_CTL_VDD3ON; in HibernateGPIORetentionDisable()
1342 if(HWREG(HIB_CTL) & HIB_CTL_VDD3ON) in HibernateGPIORetentionGet()