Lines Matching refs:HWREG
227 HWREG(ulBase + I2C_O_MTPR) = ulTPR; in I2CMasterInitExpClk()
233 if(HWREG(ulBase + I2C_O_PP) & I2C_PP_HS) in I2CMasterInitExpClk()
237 HWREG(ulBase + I2C_O_MTPR) = I2C_MTPR_HS | ulTPR; in I2CMasterInitExpClk()
274 HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; in I2CSlaveInit()
316 HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; in I2CSlaveAddressSet()
325 HWREG(ulBase + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ucSlaveAddr; in I2CSlaveAddressSet()
353 HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE; in I2CMasterEnable()
378 HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |= in I2CSlaveEnable()
384 HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveEnable()
409 HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE); in I2CMasterDisable()
434 HWREG(ulBase + I2C_O_SCSR) = 0; in I2CSlaveDisable()
439 HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &= in I2CSlaveDisable()
554 HWREG(ulBase + I2C_O_MIMR) = 1; in I2CMasterIntEnable()
591 HWREG(ulBase + I2C_O_MIMR) |= ulIntFlags; in I2CMasterIntEnableEx()
616 HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; in I2CSlaveIntEnable()
654 HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags; in I2CSlaveIntEnableEx()
679 HWREG(ulBase + I2C_O_MIMR) = 0; in I2CMasterIntDisable()
710 HWREG(ulBase + I2C_O_MIMR) &= ~ulIntFlags; in I2CMasterIntDisableEx()
735 HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; in I2CSlaveIntDisable()
766 HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags; in I2CSlaveIntDisableEx()
799 return((HWREG(ulBase + I2C_O_MMIS)) ? true : false); in I2CMasterIntStatus()
803 return((HWREG(ulBase + I2C_O_MRIS)) ? true : false); in I2CMasterIntStatus()
837 return(HWREG(ulBase + I2C_O_MMIS)); in I2CMasterIntStatusEx()
841 return(HWREG(ulBase + I2C_O_MRIS)); in I2CMasterIntStatusEx()
875 return((HWREG(ulBase + I2C_O_SMIS)) ? true : false); in I2CSlaveIntStatus()
879 return((HWREG(ulBase + I2C_O_SRIS)) ? true : false); in I2CSlaveIntStatus()
921 ulValue = HWREG(ulBase + I2C_O_SRIS); in I2CSlaveIntStatusEx()
922 return(ulValue & HWREG(ulBase + I2C_O_SIMR)); in I2CSlaveIntStatusEx()
926 return(HWREG(ulBase + I2C_O_SMIS)); in I2CSlaveIntStatusEx()
931 return(HWREG(ulBase + I2C_O_SRIS)); in I2CSlaveIntStatusEx()
968 HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC; in I2CMasterIntClear()
975 HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC; in I2CMasterIntClear()
1015 HWREG(ulBase + I2C_O_MICR) = ulIntFlags; in I2CMasterIntClearEx()
1051 HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC; in I2CSlaveIntClear()
1091 HWREG(ulBase + I2C_O_SICR) = ulIntFlags; in I2CSlaveIntClearEx()
1124 HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive; in I2CMasterSlaveAddrSet()
1154 return(HWREG(ulBase + I2C_O_MBMON)); in I2CMasterLineStateGet()
1181 if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY) in I2CMasterBusy()
1216 if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY) in I2CMasterBusBusy()
1276 HWREG(ulBase + I2C_O_MCS) = ulCmd; in I2CMasterControl()
1306 ulErr = HWREG(ulBase + I2C_O_MCS); in I2CMasterErr()
1353 HWREG(ulBase + I2C_O_MDR) = ucData; in I2CMasterDataPut()
1379 return(HWREG(ulBase + I2C_O_MDR)); in I2CMasterDataGet()
1411 HWREG(ulBase + I2C_O_MCLKOCNT) = ulValue; in I2CMasterTimeoutSet()
1443 HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1447 HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1478 HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1482 HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1530 return(HWREG(ulBase + I2C_O_SCSR)); in I2CSlaveStatus()
1556 HWREG(ulBase + I2C_O_SDR) = ucData; in I2CSlaveDataPut()
1582 return(HWREG(ulBase + I2C_O_SDR)); in I2CSlaveDataGet()