Lines Matching refs:HWREG
79 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxEnable()
84 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN; in I2STxEnable()
111 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN; in I2STxDisable()
157 while(HWREG(ulBase + I2S_O_TXLEV) >= 16) in I2STxDataPut()
164 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPut()
210 if(HWREG(ulBase + I2S_O_TXLEV) < 16) in I2STxDataPutNonBlocking()
212 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPutNonBlocking()
277 HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; in I2STxConfigSet()
286 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxConfigSet()
294 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxConfigSet()
335 HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel; in I2STxFIFOLimitSet()
362 return(HWREG(ulBase + I2S_O_TXLIMIT)); in I2STxFIFOLimitGet()
396 return(HWREG(ulBase + I2S_O_TXLEV)); in I2STxFIFOLevelGet()
423 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2SRxEnable()
428 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN; in I2SRxEnable()
455 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN; in I2SRxDisable()
500 while(HWREG(ulBase + I2S_O_RXLEV) == 0) in I2SRxDataGet()
507 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGet()
552 if(HWREG(ulBase + I2S_O_RXLEV) != 0) in I2SRxDataGetNonBlocking()
554 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGetNonBlocking()
607 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2SRxConfigSet()
614 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2SRxConfigSet()
622 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2SRxConfigSet()
637 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2SRxConfigSet()
679 HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel; in I2SRxFIFOLimitSet()
707 return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); in I2SRxFIFOLimitGet()
741 return(HWREG(ulBase + I2S_O_RXLEV)); in I2SRxFIFOLevelGet()
769 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxRxEnable()
774 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2STxRxEnable()
779 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN; in I2STxRxEnable()
806 HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN); in I2STxRxDisable()
857 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxRxConfigSet()
858 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2STxRxConfigSet()
865 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2STxRxConfigSet()
874 HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS; in I2STxRxConfigSet()
875 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2STxRxConfigSet()
883 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxRxConfigSet()
884 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2STxRxConfigSet()
921 ulConfig = HWREG(ulBase + I2S_O_CFG) & in I2SMasterClockSelect()
923 HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock; in I2SMasterClockSelect()
958 HWREG(ulBase + I2S_O_IM) |= ulIntFlags; in I2SIntEnable()
989 HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags; in I2SIntDisable()
1022 return(HWREG(ulBase + I2S_O_MIS)); in I2SIntStatus()
1026 return(HWREG(ulBase + I2S_O_RIS)); in I2SIntStatus()
1068 HWREG(ulBase + I2S_O_IC) = ulIntFlags; in I2SIntClear()