Lines Matching refs:HWREG
184 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet()
214 return(HWREG(ulBase + UART_O_LCRH) & in UARTParityModeGet()
258 HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; in UARTFIFOLevelSet()
293 ulTemp = HWREG(ulBase + UART_O_IFLS); in UARTFIFOLevelGet()
370 HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; in UARTConfigSetExpClk()
383 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); in UARTConfigSetExpClk()
394 HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; in UARTConfigSetExpClk()
395 HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; in UARTConfigSetExpClk()
400 HWREG(ulBase + UART_O_LCRH) = ulConfig; in UARTConfigSetExpClk()
405 HWREG(ulBase + UART_O_FR) = 0; in UARTConfigSetExpClk()
460 ulInt = HWREG(ulBase + UART_O_IBRD); in UARTConfigGetExpClk()
461 ulFrac = HWREG(ulBase + UART_O_FBRD); in UARTConfigGetExpClk()
467 if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) in UARTConfigGetExpClk()
479 *pulConfig = (HWREG(ulBase + UART_O_LCRH) & in UARTConfigGetExpClk()
507 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTEnable()
512 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | in UARTEnable()
539 while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) in UARTDisable()
546 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTDisable()
551 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | in UARTDisable()
577 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTFIFOEnable()
602 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTFIFODisable()
641 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); in UARTEnableSIR()
645 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN); in UARTEnableSIR()
681 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); in UARTDisableSIR()
717 ulVal = HWREG(ulBase + UART_O_LCRH); in UARTSmartCardEnable()
721 HWREG(ulBase + UART_O_LCRH) = ulVal; in UARTSmartCardEnable()
726 HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART; in UARTSmartCardEnable()
757 HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART; in UARTSmartCardDisable()
798 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlSet()
800 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlSet()
841 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlClear()
843 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlClear()
874 return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); in UARTModemControlGet()
905 return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | in UARTModemStatusGet()
947 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet()
980 return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | in UARTFlowControlGet()
1022 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet()
1059 return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | in UARTTxIntModeGet()
1087 return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); in UARTCharsAvail()
1114 return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); in UARTSpaceAvail()
1147 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) in UARTCharGetNonBlocking()
1152 return(HWREG(ulBase + UART_O_DR)); in UARTCharGetNonBlocking()
1188 while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) in UARTCharGet()
1195 return(HWREG(ulBase + UART_O_DR)); in UARTCharGet()
1230 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) in UARTCharPutNonBlocking()
1235 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPutNonBlocking()
1276 while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) in UARTCharPut()
1283 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPut()
1312 HWREG(ulBase + UART_O_LCRH) = in UARTBreakCtl()
1314 (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : in UARTBreakCtl()
1315 (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); in UARTBreakCtl()
1344 return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); in UARTBusy()
1475 HWREG(ulBase + UART_O_IM) |= ulIntFlags; in UARTIntEnable()
1506 HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); in UARTIntDisable()
1539 return(HWREG(ulBase + UART_O_MIS)); in UARTIntStatus()
1543 return(HWREG(ulBase + UART_O_RIS)); in UARTIntStatus()
1584 HWREG(ulBase + UART_O_ICR) = ulIntFlags; in UARTIntClear()
1620 HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; in UARTDMAEnable()
1652 HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; in UARTDMADisable()
1683 return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); in UARTRxErrorGet()
1712 HWREG(ulBase + UART_O_ECR) = 0; in UARTRxErrorClear()
1749 HWREG(ulBase + UART_O_CC) = ulSource; in UARTClockSourceSet()
1780 return(HWREG(ulBase + UART_O_CC)); in UARTClockSourceGet()
1809 HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; in UART9BitEnable()
1838 HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; in UART9BitDisable()
1874 HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S; in UART9BitAddrSet()
1875 HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S; in UART9BitAddrSet()
1914 while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) in UART9BitAddrSend()
1921 ulLCRH = HWREG(ulBase + UART_O_LCRH); in UART9BitAddrSend()
1922 HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS | in UART9BitAddrSend()
1928 HWREG(ulBase + UART_O_DR) = ucAddr; in UART9BitAddrSend()
1933 while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) in UART9BitAddrSend()
1940 HWREG(ulBase + UART_O_LCRH) = ulLCRH; in UART9BitAddrSend()