Lines Matching refs:HWREG
70 HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; in uDMAEnable()
89 HWREG(UDMA_CFG) = 0; in uDMADisable()
109 return(HWREG(UDMA_ERRCLR)); in uDMAErrorStatusGet()
129 HWREG(UDMA_ERRCLR) = 1; in uDMAErrorStatusClear()
160 HWREG(UDMA_ENASET) = 1 << (ulChannelNum & 0x1f); in uDMAChannelEnable()
187 HWREG(UDMA_ENACLR) = 1 << (ulChannelNum & 0x1f); in uDMAChannelDisable()
215 return((HWREG(UDMA_ENASET) & (1 << (ulChannelNum & 0x1f))) ? true : false); in uDMAChannelIsEnabled()
251 HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable; in uDMAControlBaseSet()
272 return((void *)HWREG(UDMA_CTLBASE)); in uDMAControlBaseGet()
293 return((void *)HWREG(UDMA_ALTBASE)); in uDMAControlAlternateBaseGet()
327 HWREG(UDMA_SWREQ) = 1 << (ulChannelNum & 0x1f); in uDMAChannelRequest()
374 HWREG(UDMA_USEBURSTSET) = 1 << ulChannelNum; in uDMAChannelAttributeEnable()
383 HWREG(UDMA_ALTSET) = 1 << ulChannelNum; in uDMAChannelAttributeEnable()
391 HWREG(UDMA_PRIOSET) = 1 << ulChannelNum; in uDMAChannelAttributeEnable()
399 HWREG(UDMA_REQMASKSET) = 1 << ulChannelNum; in uDMAChannelAttributeEnable()
447 HWREG(UDMA_USEBURSTCLR) = 1 << ulChannelNum; in uDMAChannelAttributeDisable()
456 HWREG(UDMA_ALTCLR) = 1 << ulChannelNum; in uDMAChannelAttributeDisable()
464 HWREG(UDMA_PRIOCLR) = 1 << ulChannelNum; in uDMAChannelAttributeDisable()
472 HWREG(UDMA_REQMASKCLR) = 1 << ulChannelNum; in uDMAChannelAttributeDisable()
516 if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannelNum)) in uDMAChannelAttributeGet()
524 if(HWREG(UDMA_ALTSET) & (1 << ulChannelNum)) in uDMAChannelAttributeGet()
532 if(HWREG(UDMA_PRIOSET) & (1 << ulChannelNum)) in uDMAChannelAttributeGet()
540 if(HWREG(UDMA_REQMASKSET) & (1 << ulChannelNum)) in uDMAChannelAttributeGet()
609 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelControlSet()
621 pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); in uDMAChannelControlSet()
721 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelTransferSet()
737 pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); in uDMAChannelTransferSet()
869 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelScatterGatherSet()
884 pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); in uDMAChannelScatterGatherSet()
946 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelSizeGet()
958 pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); in uDMAChannelSizeGet()
1016 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelModeGet()
1028 pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); in uDMAChannelModeGet()
1107 HWREG(UDMA_CHASGN) |= ulSecPeriphs; in uDMAChannelSelectSecondary()
1164 HWREG(UDMA_CHASGN) &= ~ulDefPeriphs; in uDMAChannelSelectDefault()
1279 return(HWREG(UDMA_CHIS)); in uDMAIntStatus()
1314 HWREG(UDMA_CHIS) = ulChanMask; in uDMAIntClear()
1374 HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | in uDMAChannelAssign()