Lines Matching refs:writel
68 writel(readl(DEMCR) | DEMCR_TRCENA, DEMCR); in lpc43xx_debug_early_init()
70 writel((1 << 9) | (1 << 16) | (2 << 10), DWT_CTRL); in lpc43xx_debug_early_init()
73 writel((__lpc43xx_main_clock_mhz / 6000000) - 1, TPI_ACPR); in lpc43xx_debug_early_init()
74 writel(2, TPI_SPPR); in lpc43xx_debug_early_init()
75 writel(0x100, TPI_FFCR); in lpc43xx_debug_early_init()
78 writel(0xC5ACCE55, ITM_LAR); // unlock regs in lpc43xx_debug_early_init()
79 writel(0x0001000D, ITM_TCR); // ID=1, enable ITM, SYNC, DWT events in lpc43xx_debug_early_init()
80 writel(0xFFFFFFFF, ITM_TER); // enable all trace ports in lpc43xx_debug_early_init()
85 writel(BASE_CLK_SEL(CLK_IRC), base_uart_clk[TARGET_DEBUG_UART - 1]); in lpc43xx_debug_early_init()
86 writel(LCR_DLAB, UART_BASE + REG_LCR); in lpc43xx_debug_early_init()
87 writel(4, UART_BASE + REG_DLL); in lpc43xx_debug_early_init()
88 writel(0, UART_BASE + REG_DLM); in lpc43xx_debug_early_init()
89 writel(FDR_DIVADDVAL(5) | FDR_MULVAL(8), UART_BASE + REG_FDR); in lpc43xx_debug_early_init()
92 writel(BASE_CLK_SEL(__lpc43xx_main_clock_sel), in lpc43xx_debug_early_init()
94 writel(LCR_DLAB, UART_BASE + REG_LCR); in lpc43xx_debug_early_init()
95 writel(div & 0xFF, UART_BASE + REG_DLL); in lpc43xx_debug_early_init()
96 writel((div >> 8) & 0xFF, UART_BASE + REG_DLM); in lpc43xx_debug_early_init()
98 writel(LCR_WLS_8 | LCR_SBS_1, UART_BASE + REG_LCR); in lpc43xx_debug_early_init()
99 writel(FCR_FIFOEN | FCR_RX_TRIG_1, UART_BASE + REG_FCR); in lpc43xx_debug_early_init()
100 writel(IER_RBRIE, UART_BASE + REG_IER); in lpc43xx_debug_early_init()
130 writel(c, UART_BASE + REG_THR); in platform_dputc()
157 writel(n, DCRDR); in _debugmonitor()