Lines Matching refs:i
129 unsigned int i; in mt_gic_dist_init() local
141 for (i = 32; i < (MT_NR_SPI + 32); i += 16) { in mt_gic_dist_init()
142 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16, 0); in mt_gic_dist_init()
148 for (i = 0; i < MT_NR_SPI; i++) { in mt_gic_dist_init()
149 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ROUTE + i * 8, (affinity & 0xFFFFFFFF)); in mt_gic_dist_init()
150 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ROUTE + i * 8 + 4, (affinity >> 32)); in mt_gic_dist_init()
157 for (i = 0; i < NR_IRQ_LINE; i += 32) in mt_gic_dist_init()
158 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_IGRPMODR + i / 8, 0xFFFFFFFF); in mt_gic_dist_init()
163 for (i = 0; i < NR_IRQ_LINE; i += 4) { in mt_gic_dist_init()
164 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_PRI + i * 4 / 4, 0xA0A0A0A0); in mt_gic_dist_init()
170 for (i = 0; i < NR_IRQ_LINE; i += 32) { in mt_gic_dist_init()
171 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR + i * 4 / 32, 0xFFFFFFFF); in mt_gic_dist_init()
177 for (i = 0; i < NR_IRQ_LINE; i += 32) { in mt_gic_dist_init()
178 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ACTIVE_CLEAR + i * 4 / 32, 0xFFFFFFFF); in mt_gic_dist_init()
184 for (i = 0; i < NR_IRQ_LINE; i += 32) { in mt_gic_dist_init()
185 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_PENDING_CLEAR + i * 4 / 32, 0xFFFFFFFF); in mt_gic_dist_init()
304 unsigned int i; in mt_irq_mask_all() local
307 for (i = 0; i < IRQ_REGS; i++) { in mt_irq_mask_all()
308 mask->mask[i] = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ENABLE_SET + i * 4); in mt_irq_mask_all()
309 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR + i * 4, 0xFFFFFFFF); in mt_irq_mask_all()
329 unsigned int i; in mt_irq_mask_restore() local
341 for (i = 0; i < IRQ_REGS; i++) { in mt_irq_mask_restore()
342 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_SET + i * 4, mask->mask[i]); in mt_irq_mask_restore()
352 int i; in mt_irq_register_dump() local
360 for (i = 0; i < MT_NR_SPI; i++) { in mt_irq_register_dump()
361 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ROUTE + i * 8); in mt_irq_register_dump()
362 reg2 = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ROUTE + i * 8 + 4); in mt_irq_register_dump()
363 dprintf(CRITICAL, "GICD_IROUTER[%d]: 0x%08x, 0x%08x\n", i, reg, reg2); in mt_irq_register_dump()
366 for (i = 0; i < NR_IRQ_LINE; i += 32) { in mt_irq_register_dump()
367 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_IGRPMODR + i / 8); in mt_irq_register_dump()
368 dprintf(CRITICAL, "GICD_IGRPMODR[%d]: 0x%08x\n", i >> 5, reg); in mt_irq_register_dump()
371 for (i = 0; i < NR_IRQ_LINE; i += 4) { in mt_irq_register_dump()
372 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_PRI + i * 4 / 4); in mt_irq_register_dump()
373 dprintf(CRITICAL, "GICD_IPRIORITYR[%d]: 0x%08x\n", i >> 2, reg); in mt_irq_register_dump()
376 for (i = 32; i < (MT_NR_SPI + 32); i += 16) { in mt_irq_register_dump()
377 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16); in mt_irq_register_dump()
378 dprintf(CRITICAL, "DIST_ICFGR[%d]: 0x%08x\n", (i >> 4) - 2, reg); in mt_irq_register_dump()
381 for (i = 0; i < IRQ_REGS; i++) { in mt_irq_register_dump()
382 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ENABLE_SET + i * 4); in mt_irq_register_dump()
383 dprintf(CRITICAL, "GICD_ISENABLER[%d]: 0x%08x\n", i, reg); in mt_irq_register_dump()
386 for (i = 0; i < IRQ_REGS; i++) { in mt_irq_register_dump()
387 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_PENDING_SET + i * 4); in mt_irq_register_dump()
388 dprintf(CRITICAL, "GICD_ISPENDR[%d]: 0x%08x\n", i, reg); in mt_irq_register_dump()
391 for (i = 0; i < IRQ_REGS; i++) { in mt_irq_register_dump()
392 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ACTIVE_SET + i * 4); in mt_irq_register_dump()
393 dprintf(CRITICAL, "GICD_ISACTIVER[%d]: 0x%08x\n", i, reg); in mt_irq_register_dump()